STUPIDSID
Solve any one question.Q1(a,b,c) Q2(a,b)
1(a)
Design of one bit magnitude comparator.
4 M
1(a)
Compare TTL, CMOS and ECL.
6 M
1(b)
Convert SR flip-flop to Toggle flip-flop (SR to TFF)
4 M
1(b)
Obtain an 8:1 multiplexer with a dual 4 line to 1-line multiplexers having separate enable inputs but common selections lines.
3 M
1(c)
Compare the multiplexer and de-multiplexer.
4 M
1(c)
Explain the working of CMOS Inverter.
3 M
2( b)
What do you mean by tristate logic? Explain in detail one applicaion of such logic circuit.
3 M
2(a)
Implement the following expression using single 8:1 multiplexer:
Y= ∑m (0,
1,
2,
5,
7,
8,
9,
14,
15)
Y= ∑m (0,
1,
2,
5,
7,
8,
9,
14,
15)
6 M
2(a)
Design 2-bit comparator using decoder.
6 M
2(b)
What are advantages of master-slave JK flip-flop? Explain the working with a suitable diagram.
6 M
2(c)
Explain the concept of look ahead carry generator and advantage of the same.
3 M
Solve any one question.Q3(a,b) Q4(a,b)
3(a)
Design a sequence generator for the sequence ...10110....
6 M
3(a)
Explain the following terms:
i) State Table
ii) State Diagram
iii) State Reduction.
i) State Table
ii) State Diagram
iii) State Reduction.
6 M
3(b)
Compare TTL and CMOS logic family with reference to the following characteristics:
i) fanout
ii) propagation delay
iii) Power dissipation
iv) noise margin
v) speed power product
vi) voltage and current parameters.
i) fanout
ii) propagation delay
iii) Power dissipation
iv) noise margin
v) speed power product
vi) voltage and current parameters.
6 M
3(b)
Design 4-Bit Excess-3 to BCD Code Converter and implement using Logic Gates.
6 M
4(a)
Explain the terms related to ASM chart:
i) state box
ii) decision box
iii) conditional box
i) state box
ii) decision box
iii) conditional box
6 M
4(a)
Write a short note on ALU.
5 M
4(b)
Draw aand explain working of two input TTL NAND gate and list advantages of totem pole output stage.
6 M
4(b)
By using suitable FFS design A counter to go through states 0-1-3-4-6-0. Draw the logic diagram. Examine the action of counter for the Unused States.
7 M
Solve any one question.Q5(a,b,c) Q6(a,b,c)
5(a)
A combinational circuit is defined by functions:
F1=∑m(3,
5,
7)
F2 = ∑m (4,
5,
7) Design the circuit using PLA having 3 inputs, 3product terms and 2 outputs.
F1=∑m(3,
5,
7)
F2 = ∑m (4,
5,
7) Design the circuit using PLA having 3 inputs, 3product terms and 2 outputs.
6 M
5(a)
Give comparison between PROM, PLA and PAL.
5 M
5(b)
Draw circuits of one cell of dynamic RAM and explain its working.
4 M
5(b)
A combination circuit is defined by the function :F1(A, B,C)=∑m(2, 3,7)
F2(A, B, C)=∑m(3, 4,6) Implement the Circuit using PLA.
F2(A, B, C)=∑m(3, 4,6) Implement the Circuit using PLA.
8 M
5(c)
Compare SRAM and DRAM.
3 M
6(a)
Draw and explain the internal organization of asynchronous SRAM.
6 M
6(a)
Compare between CPLD and FPGA.
6 M
6(b)
Explain PLA with the help of neat diagram.
4 M
6(b)
Design a BCD to gray code converter and implement using PLA.
7 M
6(c)
Compare CPLD and FPGA.
3 M
Solve any one question.Q7(a,b,c) Q8(a,b,c)
7(a)
Draw and explain architecture of 8051 in detail.
6 M
7(a)
Write a VHDL code for 4-Bit Binary to gray code converter using CASE statement.
8 M
7(b)
Compare the microprocessor and microcontroller.
4 M
7(b)
What is the difference between Concurrent and Sequential statement in VHDL? Explain with proper example.
5 M
7(c)
Write a program for addition of 8-bit binary numbers.
3 M
8(a)
Explain any three addressing modes of 8051 with example.
6 M
8(a)
Write a VHDL code for a 2-Bit Comparator using Data flow Modelling Technique.
7 M
8(b)
Draw and explain PSW register of 8051.
4 M
8(b)
Explain different classes of data Objects in VHDL with example for each.
6 M
8(c)
List out feature of 8051 (minimum six).
3 M
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