Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Answer any one question from Q1 and Q2
1 (a) Draw and explain the working of two input TTL NAND gates (with totem pole).
6 M
1 (b) Implement the following function using single 8 : 1 MUX.
F(A, B, C, D) = ∑m (1, 4, 6, 8, 10, 11, 13, 14)
6 M

2 (a) Design and implement full adder using suitable decoder.
6 M
2 (b) Draw and explain the working of 2 i/p CMOS NOR gate.
6 M

Answer any one question from Q3 and Q4
3 (a) Design mod 6 ripple up counter using T flip-flops.
6 M
3 (b) Convert D to T and vice versa.
6 M

4 (a) Explain Moore circuit with example. Also compare Moore and Mealy circuit.
6 M
4 (b) Design a sequence detector to detect sequence 1101 using D FF and mealy machine.
6 M

Answer any one question from Q5 and Q6
5 (a) Compare between PROM and PAL.
5 M
5 (b) A combinational circuit is defined by a function F1 = ∑m(1, 3, 5) F2= ∑m (5, ,6, 7).
Implement the circuit with PLA having 3 inputs, 3 product terms and two outputs.
8 M

6 (a) Explain in detail the architecture of CPLD.
6 M
6 (b) What is meant by EPROM ? State its advantages and disadvantages.
7 M

Answer any one question from Q7 and Q8
7 (a) Explain the following statements with examples:
i) Process
ii) Case
iii) If else.
6 M
7 (b) Write a VHDL code for 8:1 multiplexer using behavioural modelling.
7 M

8 (a) Explain in detail signal and variable with example in VHDL.
6 M
8 (b) Write a VHDL code for 4-bit ALU using case statement.
7 M

More question papers from Digital Electronics