STUPIDSID
Solve any four of the following:
1 (a)
Explain the effect on drain current due to channel length modulation and velocity saturation.
5 M
1 (b)
Implementation using CMOS inverters. \[ F=\overline{A\cdot B}=C \]
5 M
1 (c)
Draw voltage transfer characteristics for CMOS inverter and explain all regoins.
5 M
1 (d)
Give the read and write stability criteria for 6T RAM if the pull up transistors and replaced by resistors.
5 M
1 (e)
Explain low power design considerations.
5 M
2 (a)
Compare pass transistor logic, NMOS logic and CMOS logic.
10 M
2 (b)
For equal rise and tall delay five assume μn=2 μp draw an inverter equivalent circuit of 3 i/p NAND and 2 i/p XOR.
10 M
3 (a)
Compare constant voltage and constant field scaling with their merits and demerits.
10 M
3 (b)
Write short note on clock generation, stabilization and distribution.
10 M
4 (a)
Explain concept of carry look ahead with equation and how does it achieve better speed compared to ripple carry Adder.
10 M
4 (b)
Consider a CMOS inverter with following parameters
Nmos V to, n=0.6 V μn Cox=60 μA/V2 and (W/L)n=8
p mos V to, p=-0.7 V μn Cox=25 μA/V2 and (W/L)p=12
Calculate the noise margin and switching threshold (VTh) of this circuit, VDD=3V.
Nmos V to, n=0.6 V μn Cox=60 μA/V2 and (W/L)n=8
p mos V to, p=-0.7 V μn Cox=25 μA/V2 and (W/L)p=12
Calculate the noise margin and switching threshold (VTh) of this circuit, VDD=3V.
10 M
5 (a)
Implementation 4:1 multiplexer using pass transistor logic.
10 M
5 (b)
Explain concept of charge sharing and charge leakage.
10 M
Write a short notes on any three of the following:-
6 (a)
Sense amplifier
7 M
6 (b)
Array multiplier ( 4 × 4)
7 M
6 (c)
CMOS Latch up and it's prevention.
7 M
6 (d)
Resistance and capacitance estimation.
7 M
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