MU Electronics Engineering (Semester 6)
Basic VLSI Design
December 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Draw CMOS implementation of D Flip Flop.
5 M
1 (b) Implement y=A+B-C using dynamic CMOS logic.
5 M
1 (c) Explain latchup in CMOS inverter.
5 M
1 (d) Define scaling. Explain significance of scaling in VLSI circuits.
5 M

2 (a) Draw CLA (carry lookahead adder) carry chain using
i) Static CMOS logic
ii) Dynamic CMOS logic
Pseudo NMOS logic.
10 M
2 (b) Draw IT DRAM cell and explain it's read write and refresh operation.
10 M

3 (a) Explain clock generation networks and distribution networks used in VLSI circuits.
10 M
3 (b) Give and explain CMOS input & output protection circuits.
10 M

4 (a) Implement 4×4 barrel shifter using transmission gate. Explain various operation using the same.
10 M
4 (b) Explain programming techniques used for EEPROM.
10 M

5 (a) What are the drawback dynamic CMOS logic. Show the modification in dynamic CMOS logic to over come it's drawback.
10 M
5 (b) Explain operation regions of CMOS inverter with equations.
10 M

Write short notes on.
6 (a) Interconnect scaling
7 M
6 (b) Cross talk.
7 M
6 (c) Array multiplier.
7 M



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