STUPIDSID
1(a)
Draw and explain AND gate using pass transistor logic
5 M
1(b)
Explain drawback of dynamic CMOS design
5 M
1(c)
Draw and explain machester carry circuit.
5 M
1(d)
What are various programming teshniques used for EEPROM in explain them in short.
5 M
2(a)
Draw 6T SRAM cell and explain it's read and write operation.
10 M
2(b)
Define scaling? Explain various types of scaling in detail.
10 M
3(a)
Explain latch up condition in CMOS detail. What are remedies to avoid latchup.
10 M
3(b)
Give and explain the drawback of ripple carry adder. Explain 4 bit CLA adder with it's carry equations, logical network using dynamic CMOS logic.
10 M
4(a)
Explain how ESD (electrostatic discharge) affect the MOSFET. Give and explain input protection circuits.
10 M
4(b)
Give and explain interconnect scaling with its width, length, thickness and capacitances.
10 M
5(a)
Explain various technique of clock generation. Discuss 'H' tree clock distribution.
10 M
5(b)
Consider a CMOS inverter circuit with following parameters.
VDD = 3.3v VTon = 0.6v VTop = -0.7v, μnCox = 60 μ A/v2, \( \displaystyle \left ( \dfrac{W}{L} \right )_n=8 \)
μpCox = 20 μA/V2, \( \displaystyle \left ( \dfrac{W}{L} \right )_p=1.2. \) Calculate the noise margin.
VDD = 3.3v VTon = 0.6v VTop = -0.7v, μnCox = 60 μ A/v2, \( \displaystyle \left ( \dfrac{W}{L} \right )_n=8 \)
μpCox = 20 μA/V2, \( \displaystyle \left ( \dfrac{W}{L} \right )_p=1.2. \) Calculate the noise margin.
10 M
6(a)
Sense ampliter
7 M
6(b)
Barrel shifter
7 M
6(c)
Interconnect parameters.
7 M
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