STUPIDSID
Choose the correct answer:
1 (a) (i)
A device which allows the current flow in one direction but does not allow it in the opposite direction is called ____
a) Transistor
b) Filter
c) Regulator
d) Rectifier
a) Transistor
b) Filter
c) Regulator
d) Rectifier
1 M
1 (a) (ii)
The capacitance of a forward biased p-n junction is called ____
a) Diffusion
b) Conventional
c) Drift
d) Transition
a) Diffusion
b) Conventional
c) Drift
d) Transition
1 M
1 (a) (iii)
The zener power dissipation is given by the product of ____
a) VR, IZ
b) VF, IZ
c) VZ, IZ
d) None of these
a) VR, IZ
b) VF, IZ
c) VZ, IZ
d) None of these
1 M
1 (a) (iv)
The maximum efficiency of a full wave rectifier is ____
a) 40.6%
b) 60.4%
c) 78.5%
d) 81.2%
a) 40.6%
b) 60.4%
c) 78.5%
d) 81.2%
1 M
1 (b)
Explain the forward and reverse characteristics for a Ge-diode, with a neat figure.
5 M
1 (c)
With a circuit diagram, explain the working of a full wave rectifier. Draw relevant waveforms.
6 M
1 (d)
A 9V reference source is to be designed using a zener diode and a resistor connected in series to a 30V supply. Select suitable components and calculate the circuit current when the supply voltage drops to 27V. Assume IZT=200mA.
5 M
Choose the correct answer:
2 (a) (i)
A transistor is cutoff when _____
a) Both emitter and collector junction reverse biased.
b) The emitter junction is reverse biased but the collector junction is forward biased.
c) Both emitter and collector junction are forward biased.
d) The emitter junction is forward biased but the collector junction is reverse biased.
a) Both emitter and collector junction reverse biased.
b) The emitter junction is reverse biased but the collector junction is forward biased.
c) Both emitter and collector junction are forward biased.
d) The emitter junction is forward biased but the collector junction is reverse biased.
1 M
2 (a) (ii)
If α=0.95, then the value of β of the transistor is ____
a) 0.05
b) 19
c) 100
d) 120
a) 0.05
b) 19
c) 100
d) 120
1 M
2 (a) (iii)
The output characteristics of CE configuration is a graph between:
a) VBE, IB
b) VBE, VCE
c) VCE, IC
d) VBE, IE
a) VBE, IB
b) VBE, VCE
c) VCE, IC
d) VBE, IE
1 M
2 (a) (iv)
The Q-point is also known as:
a) Open point
b) Operating point
c) D.C. point
d) A.C. point
a) Open point
b) Operating point
c) D.C. point
d) A.C. point
1 M
2 (b)
Explain the working of current amplification using transistor.
5 M
2 (c)
Explain with the help of circuit diagram the working of input and output characteristics of transistor in CB configuration.
7 M
2 (d)
For a certain transistor circuit IC=12.42mA and IB=200µA
find:
i) IE
ii) α and β of transistor.
find:
i) IE
ii) α and β of transistor.
4 M
Choose the correct answer:
3 (a) (i)
In the biasing circuit, the one which gives the most stable operating point.
a) Base bias
b) Collector to base bias
c) Voltage divider bias
d) None of these
a) Base bias
b) Collector to base bias
c) Voltage divider bias
d) None of these
1 M
3 (a) (ii)
Stability factor S for base bias circuit is ____
a) S=1+β
b) S= 1-β
c) S=1/(1-β)
d) S=1/(1+β)
a) S=1+β
b) S= 1-β
c) S=1/(1-β)
d) S=1/(1+β)
1 M
3 (a) (iii)
Diode can be used for compensation of ____
changes in voltage divider bias circuit.
a) VBE
b) VCE
c) VCC
d) VE
a) VBE
b) VCE
c) VCC
d) VE
1 M
3 (a) (iv)
In emitter bias circuit ____ is connected between emitter and ground.
a) Inductor
b) Capacitor
c) Resistor
d) Diode
a) Inductor
b) Capacitor
c) Resistor
d) Diode
1 M
3 (b)
With a circuit diagram, explain the operation of collector-to-base bias circuit.
8 M
3 (c)
The voltage divider bias circuit has VCC=15V, R1=6.8kΩ, R2=3.3kΩ, RC=900Ω, RE=900Ω and hFE=50, VBE=0.7V. Find the levels of VE, IB, IC, VCE and VC. Draw the DC load line and mark the Q-point on it.
8 M
Choose the correct answer:
4 (a) (i)
SCR is a ____ device.
a) NPN
b) PNP
c) PNPN
d) PNN
a) NPN
b) PNP
c) PNPN
d) PNN
1 M
4 (a) (ii)
SCR crowbar circuit is used for protection against
a) Under voltage
b) Over current
c) Under current
d) Over voltage
a) Under voltage
b) Over current
c) Under current
d) Over voltage
1 M
4 (a) (iii)
The intrinsic stand-off ratio of UJT ____
a) Must be less than unity
b) Must be greater than unity
c) Must be zero
d) Must be negative
a) Must be less than unity
b) Must be greater than unity
c) Must be zero
d) Must be negative
1 M
4 (a) (iv)
FET is a ____ controlled device.
a) Voltage
b) Current
c) Power
d) None of these
a) Voltage
b) Current
c) Power
d) None of these
1 M
4 (b)
Explain the working of two transistor model of SCR.
6 M
4 (c)
Explain with a neat figure the construction of a p-channel JFET.
6 M
4 (d)
Give the equivalent circuit of UJT.
4 M
Choose the correct answer:
5 (a) (i)
In an oscillator we use ____ feedback.
a) Positive
b) Negative
c) Neither
d) Unity gain
a) Positive
b) Negative
c) Neither
d) Unity gain
1 M
5 (a) (ii)
The two Barkhausen conditions to be satisfied by oscillator are ____
a) |Aβ| ≤ 1, shift = 0°
b) |Aβ| ≥ 1, shift = 0°
c) |Aβ| ≥ 1, shift = 90°
d) |Aβ| ≥ 1, shift =180°
a) |Aβ| ≤ 1, shift = 0°
b) |Aβ| ≥ 1, shift = 0°
c) |Aβ| ≥ 1, shift = 90°
d) |Aβ| ≥ 1, shift =180°
1 M
5 (a) (iii)
In a RC couple amplifier the DC component is blocked by ____
a) Load resistance RL
b) Coupling capacitor CC
c) RB
d) The transistor
a) Load resistance RL
b) Coupling capacitor CC
c) RB
d) The transistor
1 M
5 (a) (iv)
f1(fL) and f2(fH) are known as ____ frequencies.
a) half
b) half power
c) decibel
d) mid band
a) half
b) half power
c) decibel
d) mid band
1 M
5 (b)
With the help of circuit diagram, explain the working of a RC couple single stage CE amplifier.
6 M
5 (c)
List the advantages of negative feedback.
5 M
5 (d)
Calculate the value of an inductor to be used in Colpitt's oscillator to generate a frequency of 10 MHz. Assume C1=100 pF and C2=50 pF.
5 M
Choose the correct answer:
6 (a) (i)
The ideal value of CMRR is ____
a) 90 dB
b) 2×105
c) 0
d) ∞
a) 90 dB
b) 2×105
c) 0
d) ∞
1 M
6 (a) (ii)
The PSRR is generally measure in ____
a) dB
b) mV/V
c) µV/V
d) V/µs
a) dB
b) mV/V
c) µV/V
d) V/µs
1 M
6 (a) (iii)
The gain of voltage follower is ____
a) Zero
b) Infinite
c) Negative
d) Unity
a) Zero
b) Infinite
c) Negative
d) Unity
1 M
6 (a) (iv)
If we apply a square waveform to a differentiator, then we get ____ at the output.
a) Cosine wave
b) Ramp
c) Sine wave
d) Train of impulses
a) Cosine wave
b) Ramp
c) Sine wave
d) Train of impulses
1 M
6 (b)
Give the characteristics of an ideal op-amp.
5 M
6 (c)
With the help of circuit diagram, explain the working of an op-amp as an integrator.
6 M
6 (d)
Design an adder circuit using op-amp to obtain an output expression. VO=-(0.1V1+0.5V2+20V3), where V1, V2, V3 are the inputs. Select RF=10kΩ.
5 M
Choose the correct answer:
7 (a) (i)
Over modulation exists when modulation index is ____
a) 1
b) 0
c) >1
d) <1
a) 1
b) 0
c) >1
d) <1
1 M
7 (a) (ii)
The relation between carrier power and total power in an AM wave is ____
a) PC=PT(1+(m2/4))
b) PC=PT(1+(m2/2))
c) PT=PC(1+(m2/4))
d) PT=PC(1+(m2/2))
a) PC=PT(1+(m2/4))
b) PC=PT(1+(m2/2))
c) PT=PC(1+(m2/4))
d) PT=PC(1+(m2/2))
1 M
7 (a) (iii)
The amplitude of both the side bands in an AM wave is ____
a) EC2/2m
b) m2EC/2
c) mEC/2
d) m2EC2/4
a) EC2/2m
b) m2EC/2
c) mEC/2
d) m2EC2/4
1 M
7 (a) (iv)
Hexadecimal and octal numbering systems are similar for the first
a) 9 digits
b) 8 digits
c) 7 digits
d) 6 digits
a) 9 digits
b) 8 digits
c) 7 digits
d) 6 digits
1 M
7 (b)
Explain the need for modulation.
6 M
7 (c)
With the help of a block diagram, explain the working of a super heterodyne receiver.
6 M
7 (d)
Perform the following decimal subtraction using 9's complement method:
i) 49-24
ii) 321-579
i) 49-24
ii) 321-579
4 M
Choose the correct answer:
8 (a) (i)
For EX-NOR gate the output is 1 if ____
a) Even number of inputs is 0.
b) Even number of inputs is 1.
c) Odd number of inputs is 0.
d) Odd number of inputs is 1.
a) Even number of inputs is 0.
b) Even number of inputs is 1.
c) Odd number of inputs is 0.
d) Odd number of inputs is 1.
1 M
8 (a) (ii)
Which of the following are universal gates?
a) Only NOR
b) Only NAND
c) Both NOR&NAND
d) NOT, AND, OR
a) Only NOR
b) Only NAND
c) Both NOR&NAND
d) NOT, AND, OR
1 M
8 (a) (iii)
The result of binary addition 1+1+1 is ____
a) carry 0, sum 0
b) carry 0, sum 1
c) carry 1, sum 0
d) carry 1, sum 1
a) carry 0, sum 0
b) carry 0, sum 1
c) carry 1, sum 0
d) carry 1, sum 1
1 M
8 (a) (iv)
A half adder has ____ inputs and outputs.
a) 1,1
b) 1,2
c) 2,1
d) 2,2
a) 1,1
b) 1,2
c) 2,1
d) 2,2
1 M
8 (b)
State DeMorgan's theorem
4 M
8 (c)
Simplify the following Boolean expressions:
i) Y=AB+A'C+BC
ii) Y=(A+B'+C')(A+B'+C)
iii) Y=C(B+C)(A+B+C)
i) Y=AB+A'C+BC
ii) Y=(A+B'+C')(A+B'+C)
iii) Y=C(B+C)(A+B+C)
6 M
8 (d)
What is a full adder? Give its truth-table, implement the full adder using logic gates.
6 M
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