MU Information Technology (Semester 3)
Analog & Digital Circuits
December 2011
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Perform 492(10) - 275(10) in BCD using 10's complement
5 M
1(b)(i) Simplify: (B+BC)(B+BC)(B+D)
2 M
1(b)(ii) Simplify ? m (0, 1,2,3,5,7, 8, 9, 10, 12, 13) using K-map
2 M
1(c) Implement the following using decoder
f1 (A,B,C) = ? m(0,4,7) + d(2,3)
f2 (A,B,C) = ? m(1,5,6)
f3 (A,B,C) = ? m(0,2,4,6)
3 M
1(d)(i) Write the truth table and excitation table of JK flip flop.
4 M
1(d)(ii) Briefly explain CAD tools for Digital Design.
4 M

2(a) Minimize ? m(0,1,2,8,9,15,17,21,24,25,27,31) using Quine-McCluskey method. Also find most essential prime implicants.
10 M
2(b) Prove that NAND and NOR are universal gates.
10 M

3(a) Design a BCD adder.
10 M
3(b) Implement Full adder using 8:1 MUX
10 M

4(a) Design MOD 12 synchronous counter using JK flip flop.
10 M
4(b) Convert: -
SR to D F/F
JK to T F/F
10 M

5(a) Given the logic expression AB + AC + C + AD + ABC + ABC
(i) Express in standard SOP form
(ii) Minimize using K-map and realise using only NAND gates.
12 M
5(b) Implement following using only one 8:1 MUX and few gates.
8 M

6(a) Design 4-bit asynchronous up/down counter.
10 M
6(b) Explain 4-bit bidirectional shift register. What are the uses of register?
10 M

Write short notes on any two of the following:-
7(a) ALU
10 M
7(b) Priority Encoder
10 M
7(c) PAL and PLA
10 M
7(d) VHDL features
10 M

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