Solve any five.

1 (a)
Convert:

i) (174.03125)

ii) Make subtraction using 2's complement method (52)

i) (174.03125)

_{10}in octal number and (DB, 94)_{16}in binaryii) Make subtraction using 2's complement method (52)

_{10}- (65)_{10}
4 M

1 (b)
Compare Schottky barrier diode and PN junction diode.

4 M

1 (c)
Derive the relation between α and β.

4 M

1 (d)
List the ideal characteristics of OPAMP.

4 M

1 (e)
Prove that NAND gate is universal gate.

4 M

1 (f)
Convert T-FF to D-FF.

4 M

2 (a)
Draw block diagram of a shunt voltage regulator and explain the working.

4 M

2 (b)
Derive the expression for the stability factor 'S' of a voltage divider bias circuit.

8 M

2 (c)
Draw circuit diagram of differentiate using OPAMP and explain.

8 M

3 (a)
Explain inverting summing amplifier using OPAMP. Derive the expression for output voltage.

8 M

3 (b)
\( \text{Y = ABC}+\text{B}\overline{\text C}\text D + \overline {\text A}\text{BC} \) simplify this equation and realize using basic gates.

4 M

3 (c)
Minimize the following expression using K-map Y=∑m(1, 2, 9, 10, 11, 14, 15). Implement the circuit using minimum number of gates.

8 M

4 (a)
Design on 8 bit comparator using IC 7485.

8 M

4 (b)
Implement the following function using 8:1 Mux

F(A, B, C, D) = ∑m(0, 1, 2, 4, 6, 9, 12, 14).

F(A, B, C, D) = ∑m(0, 1, 2, 4, 6, 9, 12, 14).

4 M

4 (c)
What is shift register? Mention different modes of operation of shift register.

8 M

5 (a)
What are advantages of VHDL. Write VHDL program for full adder.

8 M

5 (b)
Design 4 bit synchronous up counter using T-FF.

8 M

5 (c)
Draw the circuit of JK FF using NAND gates and write the truth table.

4 M

6 (a)
Design on astable multivibrator using IC 555 timer to generate an output of 1KHz with 60% duty cycle.

5 M

6 (b)
Draw the circuit diagram of regulated power supply to produce out put voltage of +5V.

5 M

6 (c)
Draw drain characteristics of n-channel JFET and explain various regions.

5 M

6 (d)
What is excess 3 code? Why it is called self complementary code?

5 M

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