SPPU Information Technology (Semester 4)
Processor Architectures & Interfacing
May 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Answer any one question from Q1 and Q2
1 (a) Differentiate between procedure and macro.
6 M
1 (b) Explain difference between 80386 pipelined and non-pipelined bus cycle with neat diagram.
6 M

2 (a) Explain the following assembler directives:
(i) Public and Extrn
(ii) .Org
(iii) : Model
6 M
2 (b) State and explain the significance of any three interrupt related signals of the 80386.
6 M

Answer any one question from Q3 and Q4
3 (a) Draw and explain the logical address to physical address translation with paging in 80386 processor.
6 M
3 (b) What is virtual mode ? How to switch from protected mode to virtual 86 mode.
6 M

4 (a) Write down the steps to switch from Real Mode (RM) to Protected Mode (PM).
6 M
4 (b) Explain the difference between 3 operating models of 80386.
6 M

Answer any one question from Q5 and Q6
5 (a) Identify and justify addressing mode of the following 8051 Instructions:
(i) MOV @ RO, A
(ii) MOV B, 50H
(iii) DIV AB.
6 M
5 (b) List SFR?s used in 8051. Draw and explain SCON and TCON.
7 M

6 (a) Explain the following instructions in 8051:
(i) MUL AB
(ii) SWAP A
(iii) MOV.DPTR, #3000H
6 M
6 (b) List the features of 8051 microcontroller. Draw and explain architecture of 8051.
7 M

Answer any one question from Q7 and Q8
7 (a) How many interrupts are there in 8051? List them according to their priority. Explain the IP register structure.
7 M
7 (b) Explain any two operating modes of timer used in 8051.
7 M

8 (a) List and classify 8051 interrupts.
7 M
8 (b) Draw and explain formats of SBUF and IE.
6 M



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