SPPU Information Technology (Semester 4)
Processor Architectures & Interfacing
December 2014
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Answer any one question from Q1 and Q2
1 (a) State instruction example for the following addressing modes of 80386 showing physical address generation:
(i) Direct
(ii) Based indexed
(iii) Scale indexed with displacement.
6 M
1 (b) Draw the general segment descriptor format. Explain how G (granularity) bit affects the LIMIT field.
6 M

2 (a) Compare and contrast:
(i) .COM and .EXE
(ii) NEAR procedure and FAR procedure.
6 M
2 (b) Explain with suitable control signals, the timing diagram of a non-pipelined write cycle of the 80386 processor.
6 M

Answer any one question from Q3 and Q4
3 (a) Draw and explain Programmer's model of 80386 in protected mode operation.
6 M
3 (b) What is privileged instruction ? Explain two examples of it.
6 M

4 (a) State and explain the difference between all operating modes of 80386.
6 M
4 (b) Explain IDT of 80386 in detail wih diagram and format.
6 M

Answer any one question from Q5 and Q6
5 (a) Draw and explain Architecture of 8051 Microcontroller.
7 M
5 (b) Explain any three addressing modes in 8051 microcontroller with example.
6 M

6 (a) Explain the following instructions in 8051:
i) ORL A, #36
ii) MUL AB
iii) SWAP A.
6 M
6 (b) Explain program status word (PSW) in 8051 microcontroller.
7 M

Answer any one question from Q7 and Q8
7 (a) State and explain SFR's required for serial communication in 8051 microcontroller.
7 M
7 (b) Draw and explain TCON and TMOD SFR's of 8051 microcontroller.
6 M

8 (a) List and explain an two operating modes of Timer of 8051.
7 M
8 (b) Explain different types of interrupt in 8051.
6 M



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