VTU Microelectronics Circuits - June 2013 Exam Question Paper

VTU Electronics and Communication Engineering (Semester 6)
Microelectronics Circuits
June 2013

Total marks: --
Total time: --

INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) Derive the equation for finite output resistance of a MOSFET.

8 M

1 (b) For the CS-amplifier shown in Fig Q1(b), find R_in Av₀, R_out and Gv with r₀ taken into account. If V_sig is a 0.4 (P-P) what output signal results? Assume R_sig=10KΩ, R₁=15KΩ, g_m=1 mA/v and r_o=150KΩ

8 M

1 (c) What is threshold voltage and mention its range?

4 M

2 (a) Draw the development of the T-equivalent circuit model for the MOSFET.

5 M

2 (b) Derive the voltage gain and overall voltage equations of a source follower using MOSFET.

8 M

2 (c) Design the circuit shown in Fig. Q2(c) so that the transistor operates at I_D=0.4 mA and V_D=0.5V, The NMOS transistor has V_t=0.7V. μ_n C_ox=100 μ A/V², L=1μm and W=32 μm. Neglect the channel length modulation effect.

7 M

3 (a) What is MOSFET scaling? Mention the benefits of scaling.

6 M

3 (b) Draw the MOSFET constant current source circuit and explain it.

6 M

3 (c) Explain the operation of a MOS current steering circuit and mention it advantage.

8 M

4 (a) What is cascade amplifier? Explain the operation of a MOS cascade amplifier.

7 M

4 (b) Draw the high frequency-equivalent circuit model of the MOSFET, common source amplifier and explain the significance of each element.

7 M

4 (c) Draw the three different transistor pairings and explain each configuration.

6 M

5 (a) Explain the operation of MOS differential pair with a differential input voltage.

7 M

5 (b) Draw the circuit diagram of a active-loaded MOS differential pair and explain it.

8 M

5 (c) What are the features of two-stage CMOS op-amp configuration?

5 M

6 (a) Explain the effect of feedback on the amplifier poles.

6 M

6 (b) What are the properties of negative feedbacks? Explain in detail.

8 M

6 (c) Draw the ideal structure for the series-series feedback amplifier and explain it.

6 M

7 (a) Explain how to minimize the temperature in a logarithmic amplifier.

8 M

7 (b) Draw the sample and hold circuit using op-amp and explain it.

7 M

7 (c) Design a non-inverting op-amp with a gain of 2. At the maximum output voltage of 10V and the current in the voltage divider is to be 10μA.

5 M

8 (a) What are the reasons for choosing CMOS over bipolar technology in digital applications?

4 M

8 (b) Explain the dynamic operation of a CMOS inverter.

10 M

8 (c) Implement F=AB+CD using the AOI gate.

6 M

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