STUPIDSID
1 (a)
Derive expression for drain current of a MOSFET in different regions of operation.
6 M
1 (b)
Design a circuit of Fig Q1(b). so that the transistor operates at ID=0.4mA and VD=±0.5V. The NMOS transistor has Vt-0.7V, μnCox=100μA/V2, L=1μm and W==32 μm. Neglect channel length modulation effect (λ=0).
4 M
1 (c)
Draw the small signal circuit model to MOSFET when |VSB|?0 and explain briefly. (ie including the body effect).
4 M
1 (d)
For the common drain amplifier stage, draw the small signal equivalent circuit and drive expression for Av, Avo, Gv Rin and Rout.
6 M
2 (a)
Compare and explain the important characteristics of NMOS and NPN transistors.
5 M
2 (b)
With a neat circuit diagram and equations explain the basic BJT current steering circuits.
5 M
2 (c)
For the high frequency equivalent circuit of common source amplifier in Fig. Q2(c). find the midband voltage gain Am=Vo/Vsig and upper 3dB frequency In using open circuit time constants.
Where RL1=3.3 KΩ Rsig=100KΩ; Rin=420KΩ; Cgs=Cgd=1Pf, gm=4m A/V.
Where RL1=3.3 KΩ Rsig=100KΩ; Rin=420KΩ; Cgs=Cgd=1Pf, gm=4m A/V.
8 M
2 (d)
For the emitter follower biased by a constant source I, shown in Fig Q2(d) draw the high frequency equivalent circuit clearly naming all the components:
2 M
3 (a)
A CMOS common source amplifier shown in Fig Q3(a) is fabricated with W/L=100 μm/1.6 μm for all transistors. With Kn'=90 μA/V2, Kpl'=30 μA/V2, IREF=100μA, VAn=8 V/μm and VAP=12 V/μm, determine the following quantities gm1, ro1, ro2, Avo.
6 M
3 (b)
Draw the MOS cascade amplifier circuit with current source biasing. With the help of small signal equivalent circuit. Show that the cascading increase magnitude of open circuit voltage gain from Ao to Ao2.
6 M
3 (c)
Write short notes orr cascade MOS current mirror circuit.
4 M
3 (d)
Find A0 for an NMOS transistor fabricated in a 0.4μm CMOS process for which Kn'=200 μA/V2, and VA'=20V/μm. The transistor has a 0.4μm channel length and is operated with an overdrive of 0.25V. What must be W for NMOS transistor to operate at ID=100 μA? Also find ro and gm.
4 M
4 (a)
Explain the operation of MOS differential pair with a differential input voltage and derive the range of differential input for differential mode of operation.
8 M
4 (b)
Prove that \[ A_{CM}= \dfrac{-r_{o4}}{2R_{SS}} \times \dfrac {1}{1+g_{m3}r_{03}} \] for the active loaded MOS differential amplifier.
8 M
4 (c)
For that BJT differential amplifier having ?=100 matched to 10% or better, and areas that are matched to 10% or better, along with collector resistor that are matched to 2% or better, find VOS, IB and IOS. The DC bias current is 100μA.
4 M
5 (a)
Explain the operation of MOSFET as linear amplifier.
5 M
5 (b)
For the common base amplifier shown in Fig Q5(b) draw the small signal equivalent circuit and hence derive an expression for Rin, Rout and AVO.
6 M
5 (c)
A MOS differential amplifier is operated at a total current of 0.8mA, using transistors with W/L ratios of 100, Kn'=μn, Cox=0.2 mA/V2, VA=20V and RD=5kΩ. Find. VOV=(VGS-Vt), gm, ro, Ad.
5 M
5 (d)
Explain channel length modulation effect of MOSFET.
4 M
6 (a)
What are the four properties of negative feedback? Briefly explain about each property.
8 M
6 (b)
For the series shunt feedback ideal amplifier find Af, Rif and Rof.
6 M
6 (c)
Discuss the method of frequency compensation for modifying open loop gain A(s) so that the closed loop amplifier is stable, by introducing a new pole in transfer function at-sufficiently low frequency.
6 M
7 (a)
Draw the circuit diagram of basic difference amplifier and derive an expression for the output voltage Vout and differential input resistance Rid.
5 M
7 (b)
Show that the gain bandwidth product of an inverting amplifier is smaller than of a non inverting amplifier.
5 M
7 (c)
Find the output voltage of the circuit, assuming Op. Amp M1 has DC open loop gain of 1×105 and a bandwidth of 10 rad/sec, op amp M2 is an ideal op amp (Ret. Fig Q7 (c)).
6 M
7 (d)
Write a note on use of op-amp in sample and hold circuit.
4 M
8 (a)
Draw the basic structure of CMOS inverter and explain the voltage transfer characteristics of CMOS inverter.
8 M
8 (b)
Consider a CMOS inverter fabricated in a 0.25μm process for which Cox=6fF/μm2, μn Cox=115μA/V2, ΠpCox=30μA/V2, Vtn=-Vtp=0.4V and VDD=2.5V. The W/L ratio of Qn is 0.375 μm/0.25 μm and for Qp is 1.125 μm/0.25μm. ;The equivalent capacitance value is 6.25 fF. Find tPHL, tPLH and tp.
6 M
8 (c)
Explain with neat circuit diagrams about pull-up and pull-down networks and used in CMOS logic circuits.
6 M
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