Solve any four question Q1.(a,b,c,d,e,f)
1(a)
Explain the difference between Ret and RETI instructions as implemented in 8051 architecture.
5 M
1(b)
What is the maximum address range of conditional jump instructions for 8051 architecture and justify the reason for the same.
5 M
1(c)
Illustrate the circuit representation for interfacing single LED and relay to the port pins of 8051 architecture based processor.
5 M
1(d)
Explain pipellning feature in ARM7TDMI architecture . Justify advantages and disadvantages.
5 M
1(e)
Explain the significance of letters and numbers in - 'ARM7TDMI'.
5 M
1(f)
Explain the bit orientations of CPSR register for ARM7TDMI architecutre.
5 M
2(a)
Write a note on the various modes of operation of ARM7TDMI based processor.
10 M
2(b)
Explain the following 8051 architecture based instructions:
a) MOV C,
ox10
b) MULAB
c) MOVC A,
A+@ox2000
d) INC ox45
e) ANLA,
@Ro
a) MOV C,
ox10
b) MULAB
c) MOVC A,
A+@ox2000
d) INC ox45
e) ANLA,
@Ro
10 M
3(a)
With a neat circuit representation illustrate interfacing of typical 8-bit DAC to 8051 architecture based processor. Using DAC write a program in 8051 assembly to generate a triangular wave.
12 M
3(b)
Explain the programmer's model (register structure) in ARM7TDMI architecture.
8 M
4(a)
Explain the various addressing modes with suitable examples avallable in 8051-architecture.
10 M
4(b)
Using internal timers write program in 8051 assembly to generate a squre wave of 10kHz frequency and 50% duty cycle on port pin P1.0.
10 M
5(a)
Explain the following ARM7TDMI architecture based instructions as well as their implicatons. a) BL Square
b) ADD R0,
R1,
R2,
LSL#3
c) MOVEQS R1,
R0
d) LDR R8,
[R3,
#4]
e) STR R2,
[R1,
#ox100]
b) ADD R0,
R1,
R2,
LSL#3
c) MOVEQS R1,
R0
d) LDR R8,
[R3,
#4]
e) STR R2,
[R1,
#ox100]
10 M
5(b)
Write a brief note on the process of interrupts and their mechanism of acknowledgement in 8051 - architecture.
10 M
6(a)
ARM7TDMI thumb mode of operation.
7 M
6(b)
Interfacing stepper/continous motor to 8051 based microcontroller.
7 M
6(c)
Serial port and modes of operation in 8051 architecture.
6 M
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