SPPU Information Technology (Semester 3)
Computer Organization & Architecture
December 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Solve any one question fromQ.1(a,b) and Q.2(a,b,c)
1(a) Describe the computer performance parameters such as CPU time, CPI, MIPS MELOPS, Benchmark and Amdahl's law.
6 M
1(b) Explain any four addressing modes with suitable diagrams.
6 M

2(a) Multiply 0111 by 011 using booth's algorithm.
6 M
Solve any one question from Q.2(b,c
2(b) Perform the divison using non-restoring method 15/2.
6 M
2(c) Explain instruction cycle states of a processor with suitable diagram
6 M

Solve any one question fromQ3(a,b) and Q.4(a,b)
3(a) Explain sequence of events that occur in Fetch Cycle symbolically with diagram at each stage.
7 M
3(b) Explain need of cache memory and direct mapping cache organization technique.
6 M

4(a) Explain control unit and its functions along with block diagram.
7 M
4(b) How virtual memory is managed using paging and TLB?
6 M

Solve any one question fromQ5(a,b) and Q.6(a,b)
5(a) Explain MIPS pipeline with appropriate pipeline resgisters between each pipeline stage.
6 M
5(b) Describe in brief any one pipline hazard.
6 M

6(a) Explain events of Excute cycle of MIPS pipeline.
6 M
6(b) Explain basic performance issues in Pipelining.
6 M

Solve any one question fromQ.7(a,b) and Q.8(a,b)
7(a) Write about Flynn's Taxonomy for Multiple Processor Organizations.
6 M
7(b) Explain Symmetric Multiprocessor (SMP) Organization with features.
7 M

8(a) Explain benefits of clustering and its configurations.
7 M
8(b) What is Multicore Computers and explain hardware performance issues of same.
6 M



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