MU Electronics Engineering (Semester 6)
Computer Organization
December 2012
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Explain Von Neumann Architecture.
6 M
1 (b) Compare Computer Organization and Computer Architecture with example.
4 M
1 (c) Explain different Mapping techniques of Cache Memory.
10 M

2 (a) Compare and contrast DMA, programmed Input/Output and Interrupt driven Input/Output.
10 M
2 (b) Compare SRAM and DRAM.
5 M
2 (c) Compare RISC and CISC.
5 M

3 (a) Explain design of control unit with respect to Softwired and Hardwired approach.
10 M
3 (b) Explain IEEE-754 standard formats to represent floating point numbers.
10 M

4 (a) What is cache coherency? Explain different protocols to solve cache coherency.
10 M
4 (b) Explain Non-Restoring division algorithm for performing 19/4.
10 M

5 (b) What is virtual memory? Explain Role of paging and segmentation in virtual memory.
10 M
5 (a) Explain multiplication of signed numbers -13*-6 using Booths algorithm.
10 M

6 (a) Explain SPARC processor in detail.
10 M
6 (b) What is the difference between pipelining and parallelism? Show that k - stage 10 Pipelined processor has k - times speed up as compared to non - pipelined system.
10 M

Write short notes on (< b > any four )
7 (a) Wave Front arrays
5 M
7 (b) RAID Memory
5 M
7 (c) Static and dynamic data flow computers
5 M
7 (d) Systolic Arrays
5 M
7 (e) I / O processor and I / O channel
5 M
7 (f) Characteristics of two level memories
5 M



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