STUPIDSID
1 (a)
Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:
M1: 16k words, 50ns access time
M2: 1m words, 400ns access time
Assume 8 words cache blocks and set size of 256 words with the set associative mapping
(i) Show the mapping between M1 and M2
(ii) Calculate the effective access time with a cache hit ratio of h=0.95
M1: 16k words, 50ns access time
M2: 1m words, 400ns access time
Assume 8 words cache blocks and set size of 256 words with the set associative mapping
(i) Show the mapping between M1 and M2
(ii) Calculate the effective access time with a cache hit ratio of h=0.95
10 M
1 (b)
What do you mean by fetch cycle, instruction cycle, machine cycle and interrupt acknowledgement cycle? Explain in brief.
10 M
2 (b)
What is micro operation? Give some examples of four types of micro - operations.
10 M
2 (a)
Multiply (-7) and (3) by using Booths multiplication.Give the flow table of multiplication.
10 M
3 (a)
What do you mean by initialization of DMA controller? How DMA controller works? Explain with suitable block diagram.
10 M
3 (b)
What is virtual memory? Explain how the virtual address is mapped into the physical address?
10 M
4 (a)
Explain with example,
how effective address is calculated in different types of addressing modes.
10 M
4 (b)
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10 M
5 (a)
Explain any two methods of hard wired control unit.
10 M
5 (b)
Explain the Von Neumann architecture with the help of diagram.
10 M
6 (a)
With the neat flow chart,
explain the procedure for the division of the floating point numbers carried out in a computer.
10 M
6 (b)
Explain the Flynns classification of the parallel processing.
10 M
Write short notes on (any four)
7 (a)
PCI bus architecture
5 M
7 (b)
Systolic arrays
5 M
7 (c)
Compare RISC and CISC
5 M
7 (d)
IEEE 754 format
5 M
7 (e)
Programmed I/O
5 M
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