STUPIDSID
Solve any five.
1 (a)
What are the advantages of dynamics logic over static CMOS logic
4 M
1 (b)
Implement three input NOR gate using standard CMOS logic.
4 M
1 (c)
In NMOS transistor \[W=10\mu m, L=1\mu m,\mu n=500 \frac{cm^{2}}{v.sec}, cox=5×10-8F/cm2\]
4 M
1 (d)
Draw the energy band diagram of MOS capacitor along with its cross-section in
accumulation, depletion, and inversion region.
4 M
1 (e)
Explain the importance of Hardware Description Language like VHDL/Verilog in
VLSI Design.
4 M
1 (f)
What are the different sources of power dissipation in VLSI Circuits.
4 M
2 (a)
Explain the process of CMOS inverter fabrication with the help of neat sketches along with mask required.
12 M
2 (b)
Draw the layout of 2 input CMOS NAND gate using λ rules
8 M
3 (a)
Draw circuit diagram of six transistors SRAM cell and explain its reading and writing operation with respective timing diagrams
10 M
3 (b)
Explain the working of CMOS inverter with help of voltage transfer characteristics.
10 M
4 (a)
Find out voltage in each case as shown below
i)
10 M
4 (b)
Draw 4 bit × 4 bit NOR based ROM array to store the following data in respective memory location.
Also draw the layout of the same.
| Memory Address | Data |
| 1000 | 0101 |
| 0100 | 0011 |
| 0010 | 1001 |
| 0001 | 0110 |
Also draw the layout of the same.
10 M
5 (a)
Draw 4 bit decade counter using D-FF. Draw respective timing diagram and write VHDL/ Verliog description for the same.
10 M
5 (b)
Calculate the threshold voltage VTO at VSB=0, for a polysilicon gate n-channel MOS transistor, with following parameters:-
Substrate doping NA=1016cm-3<.sup>
Gate oxide thickness tox=500 A 0 and
Oxide- interface fixed charge density NOX=4 × 1010cm2
Substrate doping NA=1016cm-3<.sup>
Gate oxide thickness tox=500 A 0 and
Oxide- interface fixed charge density NOX=4 × 1010cm2
10 M
6 (a)
What is crosstalk ? Why it is necessary to consider issues related to crosstalk in integrated circuits. What are methods to minimize cross talk in integrated circuits?
10 M
6 (b)
Draw and explain the working of Array Multiplier in detail
10 M
Write notes on (any four).
7 (a)
Interconnect Scaling
5 M
7 (b)
Input and output circuits
5 M
7 (c)
Transient response of CMOS Inverter
5 M
7 (d)
Clock distribution issue in VLSI
5 M
7 (e)
Design of six- transistor SRAM cell
5 M
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