STUPIDSID
1 (a)
Implement the following function using CMOS logic
\[ Y=\overline{A+(\overline{B}\cdot D)+\overline{C}} \]
\[ Y=\overline{A+(\overline{B}\cdot D)+\overline{C}} \]
4 M
1 (b)
Design a transmission gate based OR gate and show its implementation.
4 M
1 (c)
Determine the oxide capacitance/ cm2 and the process transconductance A/v2ox=10mm and an electron mobility of \[\mu n=500cm2/V-sec, \varepsilon 0=8.85 × 1014 F/m, \varepsilon si=11.7 × \varepsilon 0, \varepsilon ox=3.9\varepsilon 0, q=1.6×10-19C\]
4 M
1 (d)
Consider an interconnect pattern having a line of width 1 unit and length of 15 units and the sheet resistance is \[R_{s}=20\Omega\]. Find the total resistance of the interconnect
4 M
1 (e)
Determine the resistivity of a sample silicon that is doped ptype with boron added at a density of 1015/cm3 the mobilities of the electron and hole are
given as \[\mun=1350cm2/V-sec \mup=400 cm2/V-sec\].
4 M
2 (a)
Draw the transfer characteristics of CMOS inverter indicating clearly '5' regions of operation and explain its working for different W/L ratios
10 M
2 (b)
Explain the twin-tub CMOS fabrication process in detail
10 M
3 (a)
Consider a CMOS inverter with following parameter :
nMOS :\[ VTon=1V, \mun Cox = 50\mu A/V2, (W/L)n=8\]
PMOS: \[V(sub>Top=1V, \mup C ox=20\mu A/V2,(W/L)p=12\]
Calculate the noise margin and switching threshold (Vth) of this circuit, the power supply voltage is VDD=3V
nMOS :\[ VTon=1V, \mun Cox = 50\mu A/V2, (W/L)n=8\]
PMOS: \[V(sub>Top=1V, \mup C ox=20\mu A/V2,(W/L)p=12\]
Calculate the noise margin and switching threshold (Vth) of this circuit, the power supply voltage is VDD=3V
10 M
3 (b)
Draw the layout of a transmission gate using \[\lambda\] based rule. Use proper colour coding and aspect ratio.
10 M
4 (a)
Draw the pseudo-nmos circuit that provide the following logic operation
a) \[f=\overline{a.b+c}\]
b) \[h=\overline{(a+b+c)x+y.z}\]
c) \[f=\overline{a+(c.[x+y.z)])}\]
a) \[f=\overline{a.b+c}\]
b) \[h=\overline{(a+b+c)x+y.z}\]
c) \[f=\overline{a+(c.[x+y.z)])}\]
10 M
4 (b)
What are the different types of fast multiplier circuits explain any one in detail
10 M
5 (a)
Draw six transitor SRAM cell. Explain its read and write operation and also discuss its design consideration.
10 M
5 (b)
Draw 1 bit full adder using.
(1) Standard CMOS logic
(2) Domino logic
(3) Dynamic logic
(4). Nora logic
(1) Standard CMOS logic
(2) Domino logic
(3) Dynamic logic
(4). Nora logic
10 M
6 (a)
Write a verilog / VHDL. Module describing two serial in serial out shift register using DFF module / entity.
10 M
6 (b)
Explain in detail about the static power dissipation, dynamic power dissipation and short circuit power dissipation in CMOS logic.
10 M
Write notes on (any four).
7 (a)
Limitation of design rule (physical limitation)
5 M
7 (b)
CMOS clock styles
5 M
7 (c)
Low power design considerations
5 M
7 (d)
Modelling of MOS transistors in SPICE
5 M
7 (e)
MOSFET parasitics
5 M
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