STUPIDSID
Solve any four:
1 (a)
Explain various lambda (λ) based layout design rules.
5 M
1 (b)
Explain effect of VDD on transfer characteristics of CMOS Inverter.
5 M
1 (c)
With the help of energy band diagram, explain working of MOS capacitor in accumulation, depletion and inversion region.
5 M
1 (d)
Explain concept of charge sharing.
5 M
1 (e)
Explain advantages of twin-tub CMOS technology over n-well and p-well and technology.
5 M
2 (a)
Write VHDL / Verilog code to implements 5-bit updown counter using D-FF.
10 M
2 (b)
Compare SRAM and DRAM cell. Draw the circuit diagram for both and explain how reading and writing operation is performed.
10 M
3 (a)
Draw voltage transfer characteristics of CMOS inverter and derive expression for VIL, VIH', VOL and VOH'.
10 M
3 (b)
Explain the clock generation and different type of clocking schemes for VLSI circuit. Also explain what do you mean by clock skew and clock jitter and how it can be estimated.
10 M
4 (a)
In CMOS inverter \[ \] load capacitance is 5pf, and VDD=5V. Find
i) Inverter threshold (VINV)
ii) High to low propagation delay (TpHL)
iii) Low to High propagation delay (tpHL).
i) Inverter threshold (VINV)
ii) High to low propagation delay (TpHL)
iii) Low to High propagation delay (tpHL).
10 M
4 (b)
Draw six transistor SRAM cell and explain various design constraints on transistor size for safe and write operations with appropriate design equations.
10 M
5 (a)
Implement clocked SR flip flop using CMOS logic and explain its working with the help of its truth table and appropriate waveforms.
10 M
5 (b)
Question are missing in original question paper.
10 M
Implement 4:1 MUX using:
6 (a) (i)
Pass transistor logic.
5 M
6 (a) (ii)
Transmission gate logic.
5 M
6 (b)
Explain the effect of interconnect scaling on various performance parameters of VLSI chip.
10 M
Write short notes on any four:
7 (a)
Cross - talk.
5 M
7 (b)
Programmable logic Array.
5 M
7 (c)
3 transistor DRAM cell.
5 M
7 (d)
NOR based ROM Array.
5 M
7 (e)
NORA logic.
5 M
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