MU Computer Engineering (Semester 6)
Advanced Microprocessor
May 2012
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) Enlist the instruction pairing rules of U and V pipeline in Pentium.
5 M
1 (b) Write a short note on Intel's Net burst micro architecture.
5 M
1 (c) Draw the data flow graph for computation of integer power Z = Xn of an input number X.
5 M
1 (d) States the use of following X 86 flags.
5 M

2 (a) Explain how the flushing of pipeline is minimize in Pentium architecture.
10 M
2 (b) Explain in brief integer instruction pipeline stages of Pentium processor. List the steps in instruction issue algorithm.
10 M

3 (a) Differentiate between Pentium and Pentium pro processor with respect to size of address /data bus, addressable memory, virtual memory, L2 cache, generation, SMP support, integer pipeline stages, no of integer pipes, floating point pipeline stages, no of floating pipes.
10 M
3 (b) State the feature of Intel Itanium processor. Draw the block diagram of Itanium processor. Explain in brief.
10 M

4 (a) Segmentation and paging in protected mode of 80386 processor.
10 M
4 (b) Explain the debug registers of 80386DX processor.
10 M

5 (a) Consider following reservation table for unipipeline function.
  0 1 2 3 4 5 6 7 8
S1 X               X
S2   X X         X  
S3       X          
S4         X X      
S5             X X  
(i) Find the forbidden set of latencies
(ii) State the collision vector
(iii) Draw the state transition diagram
(iv) List simple cycles and greed cycles
(v) Calculate MAL (maximum average latency).
10 M
5 (b) Explain static data flow computer architecture with example.
10 M

6 (a) Differentiate between real mode and protected mode of X 86 family.
10 M
6 (b) Explain cache organization of Pentium.
10 M

Write short notes on:-
7 (a) Structure of segment descriptor
5 M
7 (b) USB
5 M
7 (c) Layered architecture of SCSI
5 M
7 (d) EISA
5 M

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