STUPIDSID
1 (a)
Define computer architecture. List and explain four important technologies, which lead to the improvements in computer system.
10 M
1 (b)
Find the number of dies per 300mm (30 cm) wafer for disc that is 1.5 cm on side.
2 M
1 (c)
Define Amdahl's law. Derive an expression for CPU clock as a function of instruction count, clock per instruction and clock cycle time.
8 M
2 (a)
List three major hurdles of pipeline. Explain the concept of minimizing data hazards stalls by forwarding.
10 M
2 (b)
Briefly explain how the MIPS instructions can be implemented in at most five clock cycles.
5 M
2 (c)
List and explain five different ways of classifying exceptions in a computer system.
5 M
3 (a)
What is instruction level parallelism? Explain control dependence using code fragment.
8 M
3 (b)
Explain the states in 2 bit prediction scheme used for dynamic Brach prediction.
6 M
3 (c)
With a neat diagram, explain the basic structure of a MIPS floating pint unit using Tomasulo's algorithm.
6 M
4 (a)
With a neat diagram, explain the four steps involved in executing instruction using hardware based speculation.
10 M
4 (b)
What is branch target buffer? With a neat diagram, explain the steps when using branch target buffer for a simple five stage pipeline.
10 M
5 (a)
To achieve a speed-up of 80 with 100 processors, what fraction of the original computation can be sequential?
4 M
5 (b)
Explain the two cache coherence protocols used for enforcing coherence.
6 M
5 (c)
Explain directory based cache coherence for a distributed memory multiprocessor system along with the state transition diagram.
10 M
6 (a)
List and explain any four cache optimization techniques.
10 M
6 (b)
With a neat diagram, explain the translation buffer of fast address translation.
10 M
7 (a)
List any five advanced optimizations of cache performance and explain briefly the compiler.
10 M
7 (b)
Optimization to reduce miss rate.
Explain briefly how memory protection is enforced via virtual memory and via virtual machines.
Explain briefly how memory protection is enforced via virtual memory and via virtual machines.
10 M
8 (a)
Explain the architecture of IA64 Intel processor and also the prediction and speculation support provided.
10 M
8 (b)
Write short notes on benchmarks.
5 M
8 (c)
Explain the internal organization of 64M bit DRAM.
5 M
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