STUPIDSID
1 (a)
Define Computer Architecture. Illustrate the seven dimensions of an ISA.
8 M
1 (b)
Find the die yield for disc that are 1.5 cm on a side and 1.0 cm on a side assuming a defect density of 0.4 per cm2 and α is 4.
4 M
1 (c)
Define Amdahl's law. Derive an expression for cpu clock as a function of instruction count. Clocks per instruction and clock cycle time.
8 M
2 (a)
What is pipeline? With neat diagram, explain the classic five stage pipeline for RISC processor.
8 M
2 (b)
Consider unpipelined processor. Assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipeline the processor adds 0.2 ns of overhead to the clock. Ignoring any latency impact, how much speed-up in the instruction execution rate will we gain from pipeline?
6 M
2 (c)
Explain different techniques in reducing pipeline branch penalties.
6 M
3 (a)
Explain true data dependence, name dependence and control dependence, with an example.
5 M
3 (b)
What is Correlating Predictors? Explain with example.
5 M
3 (c)
With a neat diagram give the basic structure of Tomasulo based MIPS FP unit and explain various fields of reservation station.
10 M
4 (a)
Explain exploiting ILP using dynamic scheduling multiple issue and speculation.
8 M
4 (b)
Explain pentium 4 pipeline supporting multiple issue with speculation.
8 M
4 (c)
Explain in detail. Branch-Target buffers.
4 M
5 (a)
Explain the basic scheme for enforcing coherence in a shared memory multiprocessor system.
10 M
5 (b)
Explain the Taxonomy of parallel architecture.
5 M
5 (c)
Suppose you want to achieve a speed-up of 80 with 100 processors. What fraction of the original computation can be sequential?
5 M
6 (a)
Explain four memory hierarchy questions, in detail.
8 M
6 (b)
Explain in brief, the types of basic cache optimization.
10 M
6 (c)
Define Virtual Memory and describe its features.
2 M
7 (a)
Which are the major categories of advanced optimizations of cache performance? Explain any one in detail.
10 M
7 (b)
Describe the technique to improve memory performance inside DRAM chip.
5 M
7 (c)
Explain the processor of protecting via virtual machines.
5 M
8 (a)
Explain detecting and enhancing loop level parallelism for VLIW.
8 M
8 (b)
Explain Intel ? IA64 architecture, with a neat diagram.
8 M
8 (c)
Write a brief note on predicated instructions.
4 M
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