STUPIDSID
1 (a)
Define instruction set architecture (ISA). Explain seven dimensions of an ISA.
8 M
1 (b)
Briefly explain the Amdahl's law.
6 M
1 (c)
Suppose that we want to enhance the processor used for web serving than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement.
6 M
2 (a)
With a neat diagram, explain the classic five stage pipeline for a RISC processor.
10 M
2 (b)
Explain different techniques in reducing pipeline branch penalties.
10 M
3 (a)
Define instruction level parallelism. Explain data dependencies and different types of data hazards with examples.
8 M
3 (b)
What is correlating predictors? Explain with example.
4 M
3 (c)
Explain Tomasulo's algorithm, sketching the basic structure of a MIPS floating point unit.
8 M
4 (a)
Explain the basic VLIW approach for exploiting ILP, using multiple issues.
8 M
4 (b)
Explain branch target buffer with neat diagram.
6 M
4 (c)
What are the issues involved in implementation of speculation? Explain register renaming approach.
6 M
5 (a)
Explain the different taxonomy of parallel architecture.
6 M
5 (b)
To achieve a speedup of 80 with 100 processor what fraction of original computation can be sequential?
6 M
5 (c)
Explain the snooping, with respect to cache-coherence protocol.
8 M
6 (a)
Briefly explain six basic cache optimization methods.
12 M
6 (b)
With a neat diagram, explain the translation buffer of fast address translation.
8 M
7 (a)
Which are the major categories of advanced optimizations of cache performance? Explain any one in detail.
12 M
7 (b)
Explain DRAM memory technology with its basic organization.
8 M
8 (a)
Explain in detail, the hardware support for preserving exception behaviour during speculation.
10 M
8 (b)
Explain the architecture of IA64 intel processor and also prediction and speculation support provided.
10 M
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