SPPU Computer Engineering (Semester 8)
Advanced Computer Architecture
May 2014
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Answer any one question from Q1 and Q2
1 (a) What do you mean by Coarse grain parallelism and Fine grain parallelism? With examples of each category, explain how Multitasking OS achieves parallelism?
10 M
1 (b) Prove that 'n' stage pipeline processor can be at most 'n' times faster than a corresponding non-pipelined serial processor.
8 M

2 (a) Discuss the different ways of classifying the parallel computing systems.
10 M
2 (b) State and explain Explicitly Parallel Instruction computing (EPIC) Features.
8 M

Answer any one question from Q3 and Q4
3 (a) Consider the following line reservation table:
  0 1 2 3 4 5 6
S1 X   X       X
S2       X   X  
S3     X   X    

i) Determine latencies in the forbidden list F and Collision vector C.
ii) Draw the state transition diagram.
iii) List all simple cycles and greedy cycles.
iv) Determine minimum constant latency and minimum average latency.
v) Let the pipeline clock period be τ = 20 ns. Determine the maximum throughput of the pipeline.
10 M
3 (b) Explain the following terms with respect to pipeline processors.
i) Hazards
ii) Internal Forwarding
6 M

4 (a) With the help of suitable flowchart / diagram explain in detail branch prediction logic implemented in Pentium architecture.
8 M
4 (b) What is meant by pipeline, superscalar and super pipeline processor? What are the various factors placing constraints on new start of pipeline processes?
8 M

Answer any one question from Q5 and Q6
5 (a) With suitable example, discuss the efficiency of vector processing over scalar processing.
8 M
5 (b) Draw a 3-cube n/w as multistage network. State and obtain the permutation cycles for all the routing functions.
8 M

6 (a) Discuss characteristics of vector processors. Explain implementation of following loop in conventional scalar processor and vector processor.
DO 100
I = l, N
A (I) = B(I) + C(I)
100 B(I) = 2*A(I+1)
8 M
6 (b) Explain following pipelined vector processing methods with respect to vector summation computation. i) Vertical Processing
ii) Vector Looping
How intermediate results are handled in both the cases?
8 M

Answer any one question from Q7 and Q8
7 (a) What are the cache write policies used for cache updating? With state diagram explain the Write Once cache coherency protocol.
9 M
7 (b) List different dynamic priority arbitration algorithms used in bus based multi- processor systems and discuss any 2 such algorithms in brief.
9 M

8 (a) Compare the shared memory system architecture with distributed systems. What are the desirable processor characteristics used in multi-processor systems?
9 M
8 (b) With neat diagram explain the design of crossbar switch. Compare the crossbar switch Interconnection Network with multi-ported memory model.
9 M

Answer any one question from Q9 and Q10
9 (a) What are multi-threaded architectures? Discuss the various performance parameters of multi-threaded processor architectures.
8 M
9 (b) Compare between synchronous and asynchronous message passing.
8 M

10 (a) What is latency hiding? Explain any Two methods used for latency Hiding in multi-threaded architectures.
8 M
10 (b) With example explain message passing parallel programming. What is SPMD Programming?
8 M

Answer any one question from Q11 and Q12
11 (a) Explain following communication functions used in MPI
i) MPI_Scatter()
ii) MPI_Gather()
iii) MPI_Bcast()
iv) MPI_Allgather()
8 M
11 (b) With standard functions discuss how message passing is faciliated in PVM.
8 M

12 (a) With standard constructs discuss the important features of CCC parallel programming language.
8 M
12 (b) Compare between synchronous and asynchronous parallel algorithms for multiprocessor system and discuss standard primitives used.
8 M

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