SPPU Computer Engineering (Semester 8)
Advanced Computer Architecture
December 2014
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Answer any one question from Q1 and Q2
1 (a) Explain in brief general classification of parallel computer architectures based on following techniques.
i) Flynn's classification
ii) Feng's classification
8 M
1 (b) With suitable example/flow chart explain:
i) Branch Prediction and
ii) Speculative loading
8 M

2 (a) Define parallel processing. How parallel computer architectures are classified? Discuss the levels of parallel processing.
8 M
2 (b) What is EPIC? Explain EPIC features of Itanium processor in details.
8 M

Answer any one question from Q3 and Q4
3 (a) With the help of the block diagram explain in detail branch prediction logic implemented in Pentium architecture.
8 M
3 (b) Explain various types of data hazards observed in Pentium processor. How these hazards could be detected?
8 M

4 (a) Explain in brief register window structure of SPARC. How it supports parameter passing through procedure calls?
8 M
4 (b) Discuss the various features of UltraSPARC architecture. Explain in brief, the concept of RSE.
8 M

Answer any one question from Q5 and Q6
5 (a) Discuss with suitable example the necessity of Data routing and manipulation with respect to SIMD interconnection network. Also define data routing functions of 3 cube network.
10 M
5 (b) For a Mesh interconnection network for array processors, discuss in detail the parallel algorithm for matrix multiplication. Obtain the time complexity for the same.
8 M

6 (a) How a 3-cube network can be viewed as
i) Single stage recirculating network.
ii) Multistage network.
6 M
6 (b) Discuss parallel sorting algorithm for array processors and obtain its time complexity.
6 M
6 (c) With suitable example explain following features implemented in cray-1 architecture.
i) Vector chaining.
ii) Vector looping
6 M

Answer any one question from Q7 and Q8
7 (a) What is the difference between static and dynamic bus arbitration techniques. Explain any two dynamic bus arbitration techniques.
8 M
7 (b) Explain in brief desirable processor characteristics for multiprocessor architecture.
8 M

8 (a) Explain features of IBM Power 4 Processor.
8 M
8 (b) Explain time shared bus as an interconnection network for multiprocessor systems. Discuss daisy chaining arbitration algorithm, with neat diagram.
8 M

Answer any one question from Q9 and Q10
9 (a) Discuss the various context switching policies implemented in multithreaded architecture.
8 M
9 (b) Explain with suitable example shared memory parallel programming.
8 M

10 (a) Discuss different latency hiding techniques used in multithreading architectures.
8 M
10 (b) Explain in brief the following with respect to multithreading:
i) Latency.
ii) Context switched overhead.
iii) Interleaved multithreading.
iv) Number of threads.
8 M

Answer any one question from Q11 and Q12
11 (a) Discuss the issues in multiprocessor operating system? Discuss in detail.
10 M
11 (b) What is the difference between grid computing and cluster computing? Discuss features of grid computing.
8 M

12 (a) What are various performance measures for the parallel algorithms?
6 M
12 (b) Comment on PThreads (parallel threads) in shared memory system?
6 M
12 (c) What are the major features of FOR TRAN-90 to be qualified as parallel programming language?
6 M



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