STUPIDSID
1 (a)
Explain with a neat diagram, enhancement mode transistor action of MOS transistor.
8 M
1 (b)
Using neat diagram, describe fabrication steps for n-MOS transistor.
8 M
1 (c)
Compare CMOS and Bipolar technologies.
4 M
2 (a)
What do you mean by Lambda (λ) based design rule? Explain, indicate and draw design for PMOS, CMOS and n-mos.
12 M
2 (b)
Using CMOS logic draw schematic and Layout diagram for Y= AB+CD .
8 M
3 (a)
Explain why p-MOS and n-MOS has been used in CMOS complementary logic. Discuss CMOS complementary logic with an example.
6 M
3 (b)
Describe the following logic structures with an example.
i) Pseudo-n-MOS logic
ii) Dynamic CMOS logic
i) Pseudo-n-MOS logic
ii) Dynamic CMOS logic
10 M
3 (c)
Using Bi-CMOS logic structure design a schematic circuit for h= ab+c.
4 M
4 (a)
What is sheet resistance? Derive the expression for sheet resistance.
8 M
4 (b)
Explain delay unit.
6 M
4 (c)
Discuss the scaling factors for n-MOS transistor.
6 M
5 (a)
Discuss the architectural issues of CMOS subsystem design.
4 M
5 (b)
Explain combinational logic using a parity generator.
8 M
5 (c)
Explain: (i) Dynamic register element (ii) Dynamic shift register
8 M
6 (a)
Design and explain 4bit shifter using 4×4 cross bar and barrel shifter.
12 M
6 (b)
Explain with a neat diagram 4-bit serial ? parallel multiplier.
8 M
7 (a)
Explain with a neat diagram, a three transistor dynamic RAM cell.
8 M
7 (b)
Explain CMOS Pseudo ? static memory cell using circuit and stick diagram.
12 M
8 (a)
Discuss the floor plan and layout using 4-bit processor.
8 M
8 (b)
Write a short note on
i) Built ? in ? self ? test (BIST)
ii) Scan design technology.
i) Built ? in ? self ? test (BIST)
ii) Scan design technology.
12 M
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