STUPIDSID
1 (a)
Explain the fabrication steps of CMOS P-well with neat diagram and write the mask sequence.
12 M
1 (b)
List the threshold voltage equations and emphasize each terms.
8 M
2 (a)
Write the CMOS inverter circuit and briefly explain, write the CMOS VTC showing regions A, B, C, D, E. Derive the expression for output voltage in region 'B'.
10 M
2 (b)
Write the circuit and layout for Y=AB+CD+E in CMOS style.
10 M
3 (a)
Write the circuit and stick diagram for CMOS tristate inverter.
4 M
3 (b)
Write the circuit of Bi CMOS NAND and NOR gate and briefly explain.
8 M
3 (c)
Explain the circuit of dynamic CMOS logic by taking an example of the function Y=A (B+C)=DE.
8 M
4 (a)
Define Sheet Resistance (Rs) and standard unit of capacitance (μCg). Calculate the on resistance of 4:1 nmos inverter with \[ Rs=10 k\Omega/\mu , \ Z_{pu} = \dfrac {8\lambda}{2 \lambda}, \ Z_{pd}= \dfrac {2 \lambda}{2 \lambda}. \] Also estimate the total power dissipated if VDD=5V.
8 M
4 (b)
Calculate the capacitance in μ Cg for the given metal layer shown in fig. Q4 (b). If feature size=5μ5 and relative value of metal to substrate=0.075.
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5 M
4 (c)
Explain briefly the circuit of inverting and non-inverting super buffer.
7 M
5 (a)
Calculate the O/P voltage Vout in the circuit given below for different values of Va, Vb,
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| Va | Vb |
|
3.3 1.5 3.5 0 |
3.3 1.5 0 1.5 |
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4 M
5 (b)
Design Bus Arbitration for n-line bus.
10 M
5 (c)
Consider ?-based design rules and 5μm technology: How many nmos 8:1 inverter \[\left ( Z_{pu} = \dfrac {16 \lambda}{2 \lambda} \ and \ Z_{pd}= \dfrac {2 \lambda}{2 \lambda} \right ) \] can be derive by a minimum size conductor which is 3? wide and 1μ thick? Assume Jth=1 mA/(μm)2, Rs=10KΩ/μ, VDD=5V.
6 M
6 (a)
Discuss the 4 phase clocking scheme to avoid the problem of cascading in dynamic CMOS logic.
6 M
6 (b)
What are the adder enhancement techniques? Briefly explain.
4 M
6 (c)
Write and explain 6-bit carry select adder.
10 M
7 (a)
Write and explain Transistor dynamic and 6 Transistor static CMOS memory cell with sense amplifier.
12 M
7 (b)
Explain the one transistor dynamic memory cell emphasizing three plate capacitor.
8 M
Write short notes on:
8 (a)
Latch up.
7 M
8 (b)
Nature of failure in CMOS.
6 M
8 (c)
I/O pads
7 M
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