STUPIDSID
1(a)
explain the NMOS enhancement mode transistor operation for different values of Vgs and Vds.
10 M
1(b)
Explain the CMOS inverter transfer characteristics highlighting the regions of operations of the MOS transistor.
10 M
2(a)
Draw the circuit and stick diagram for the nMOS and CMOS implementation of the Boolean expression \[Y=\widehat{AB+CD}\]
10 M
3(a)
Explain the differences between ?Based_rules for (nMOS and CMOS) and transistor design rules (nMOS PMOS and CMOS).
10 M
3(b)
Explain the following: i) dynamic logic; ii) clocked CMOS logic.
12 M
4(a)
Provide scaling factors for:
i) saturation current.
ii) Current density
iii) Power dissipation / unit area.
iv) Maximum operating frequency.
i) saturation current.
ii) Current density
iii) Power dissipation / unit area.
iv) Maximum operating frequency.
10 M
4(b)
Discuss the following in scaling of MOS circuits:
i) Limits of miniaturization.
ii) Limits of interconnect and contact resistance.
i) Limits of miniaturization.
ii) Limits of interconnect and contact resistance.
10 M
5(a)
Discuss the architectural issues related to sub system design.
8 M
5(b)
Explain switch logic (nMOS and CMOS) implementation for 4-way multiplexer.
12 M
6(a)
Discuss the general arrangements of a 4- bit arithmetic processor.
12 M
6(b)
Explain 4 X 4 barrel shifter with neat diagram.
8 M
7(a)
Explain 3- transistor dynamic RAM-cell.
10 M
7(b)
Explain write operation,read operation for four transistor dynamic and six transistor static CMOS memory cell.
10 M
8(a)
Explain the scan design techniques.
10 M
8(b)
Write a note on testability and testing
10 M
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