STUPIDSID
1 (a)
Discuss the NMOS enhancement mode transistor for different conditions of vds.
6 M
1 (b)
Elaborate the concept of P-well fabrication with neat sketches.
10 M
1 (c)
Compare CMOS and bipolar technologies.
4 M
2 (a)
Obtain the transfer characteristics of a CMOS inverter and mark all the regions, showing the status of PMOS and NMOS transistors.
10 M
2 (b)
Illustrate the schematic and stick diagram for the expression Y=A(B+C).
10 M
3 (a)
Discuss in detail the λ based design for CMOS.
10 M
3 (b)
Realize a 3 input NAND gate for clocked CMOS logic and also for CMOS domino logic.
6 M
3 (c)
Discuss the working of pseudo NMOS logic with suitable example.
4 M
4 (a)
Describe the delay unit τ in terms of sheet resistance and area capacitance for the CMOS inverter pain shown, calculate the total delay.
8 M
4 (b)
Explain in brief the wiring capacitance.
6 M
4 (c)
Narrate the steps involved in calculate the sheet resistance of
i) Transistor channel
ii) nMOS inverter
iii) CMOS inverter.
i) Transistor channel
ii) nMOS inverter
iii) CMOS inverter.
6 M
5 (a)
What are the scaling factors for the following device parameters.
i) Gate capacitance cg ii) max-operating frequency f0 iii) current density iv) power dissipation per gate pg v) power speed product PT.
i) Gate capacitance cg ii) max-operating frequency f0 iii) current density iv) power dissipation per gate pg v) power speed product PT.
10 M
5 (b)
Design a parity generator with the following specifications and draw the stick diagram of one basic cell.
10 M
6 (a)
Draw the basic form of two-phase clock generator and explain in detail.
8 M
6 (b)
Discuss the architectural issues to be followed in the design of a VLSI subsystem.
6 M
6 (c)
Explain the pre-charge bus approach used in system design.
6 M
7 (a)
Explain the three transistor dynamic RAM cell.
10 M
7 (b)
Discuss the Bangh-Wooley method used for two's complement multiplication.
10 M
8 (a)
Narrate the meaning of 'Real Estate' in VLSI design.
5 M
8 (b)
Explain testing and testability in detail.
10 M
8 (c)
Write a short note on scan design techniques.
5 M
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