MU Electronics Engineering (Semester 7)
Micro Computer System Design
May 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Explain different bus phase in SCSI.
5 M
1 (b) PCI bus is called 'Green Bus' Justify.
5 M
1 (c) Explain TAP port of Pentium Processor.
5 M
1 (d) Explain Methods of Invalidating cache line for Pentium Processor.
5 M

2 (a) With respect to data cache of Pentium Processor explain cache line organization and Bank conflict in simultaneous data access.
10 M
2 (b) Explain with Neat diagram data bus steering while executing the following instruction. Assume 16-bit device interfaced to Pentium Processor. Indicate how many bus cycles are run for this operation.
MOV EAX, [4000012H].
10 M

3 (a) Explain IDE protocol for data read write command.
8 M
3 (b) Describe MESI protocol with suitable example.
12 M

4 (a) Explain how Interrupts are handled on PCI bus? Also how interrupts are routed on PCI bus.
10 M
4 (b) Describe PCI bus arbitration in detail.
10 M

5 (a) Explain following terms of USB bus
i) Host Controller and its function
ii) NAK and ACK Token
iii) Transaction Frame
10 M
5 (b) Explain following signals in SCSI, ATN, MSG, BSY, SEL, REQ, ACK.
10 M

6 (a) Describe Branch prediction Logic in Pentium Processor.
10 M
6 (b) Explain split line Access with neat diagram.
10 M

Write short notes on:
7 (a) Explain what is sector Interleave and its use in disk Drive?
7 M
7 (b) Explain USB bus topology.
7 M
7 (c) PCI Write Cycle.
7 M



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