STUPIDSID
1 (a)
Explain organization of data cache of Pentium processor and explain why it is triple ported.
10 M
1 (b)
Explain how are interrupts routed in PCI bus? Give suitable example. Also explain use of Interrupt Pin register and Interrupt Line register.
10 M
2 (a)
Explain instruction paring rules in Pentium processor
10 M
2 (b)
Explain how coherency is maintained between L 1 data cache of Puntinm Processor, L 2 cache and main memory.
10 M
3 (a)
Explain with a neat diagram data bus steering while executing 32 bit data read
instruction. Assume 16 bit device interfaced to Pentium processor.
Indicate how many bus cycles are run for this operation.
Indicate how many bus cycles are run for this operation.
12 M
3 (b)
Explain following signals in Pentium Processor INIT, LOCK#, SCYC, R/S#
8 M
4 (a)
Explain with neat diagram protocol for PIO read command in IDE.
10 M
4 (b)
Explain the difference between synchronous and asynchronous data phase in SCSI.
10 M
5 (a)
Explain the process of Device Enumeration in USB devices.
10 M
5 (b)
Explain Following signals in SCSI
ATN, MSG, BSY, REQ, ACK
ATN, MSG, BSY, REQ, ACK
10 M
6 (a)
Master A wants to perform 2 transactions as 2 data writes from device C,
2 data reads from device D
Master B wants to pcrfonn 3 data reads from device D
Master A & B request together, and priority of master B is less than that of A.
Explain transactions performed with timing diagrams.
2 data reads from device D
Master B wants to pcrfonn 3 data reads from device D
Master A & B request together, and priority of master B is less than that of A.
Explain transactions performed with timing diagrams.
12 M
6 (b)
Explain bus parking in PCI bus
8 M
7 (a)
Explain Reflected wave switching used in PCI bus.
5 M
7 (b)
Explain the use of Branch Target Buffer in Pentium processor
5 M
7 (c)
Explain methods of invalidating cache lines for Pentium processor
5 M
7 (d)
Explain different data transfer types in USB
5 M
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