MU Integrated Circuits - May 2013 Exam Question Paper

MU Electronics and Telecom Engineering (Semester 5)
Integrated Circuits
May 2013

Total marks: --
Total time: --

INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) Explain capture range, lock range and pull in time with reference to PLL

5 M

1 (b) Explain log amplifier

5 M

1 (c) List ideal characteristics of op-amp

5 M

1 (d) Explain the working of Schmitt trigger

5 M

2 (a) Explain with neat diagram the working of IC 555 as monostable multivibrator state and explain any two applications

10 M

2 (b) (i) Draw and explain block diagram of CPLD

6 M

2 (b) (ii) Give features of XC 9500 family

4 M

3 (a) Design a second order KRC band reject filter with f₀=50 Hz and bandwidth =6 Hz

10 M

3 (b) Explain in detail any two applications of instrumentaion amplifier

10 M

4 (a) Write VHDL Code for 4-bit down counter

10 M

4 (b) (i) Explain various documentation standard of sequenctial circuit

6 M

4 (b) (ii) Explain switch de-bouncing

4 M

5 (a) Explain with output derivation the working of inverting and non-inverting adder circuit

10 M

5 (b) Draw and explain the functional block diagram of IC XR-2206

10 M

6 (a) Draw the block diagram of IC 565 PLL. Explain in detail FSK demodulation using PLL

10 M

6 (b) Design a sequence detector to detect a serial input sequence of 1010. use JK Flip-Flops.

10 M

Write short notes on :-

7 (a) Dual slop A/D Converter

5 M

7 (b) LM 380 audio amplifier

5 M

7 (c) General architecture of FPGA

5 M

7 (d) V to I converter using grounded load

5 M

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