Solve any one question from Q1 and Q2

1 (a)
The following specifications are given for the DIBO differential amplifier:

R

i) Determine the I

ii) Determine the voltage gain.

R

_{E}=4.7 kΩ, R_{C}=2.2 kΩ, R_{in1}=R_{in2}=50Ω, V_{8}=±10 V and the transistor with β_{ac}=β_{dc}=100 with V_{BE}=0.7 V.i) Determine the I

_{CQ}and V_{CEQ}values.ii) Determine the voltage gain.

6 M

1 (b)
With neat circuit, explain the dominant pole frequency compensation technique.

6 M

2 (a)
Design a DIBO differential amplifier with a constant current bias using diodes to satisfy the following requirements:

Differential voltage gain Ad=±10

Current supplied by the constant bias circuit=4 mA

Supply voltage V

Differential voltage gain Ad=±10

Current supplied by the constant bias circuit=4 mA

Supply voltage V

_{S}=±12V.
6 M

2 (b)
Write a note on noise in op-amp.

6 M

Solve any one question from Q3 and Q4

3 (a)
Explain virtual ground concept and virtual short concept.

6 M

3 (b)
With neat circuit diagram and waveforms, explain working of half wave precision rectifier.

6 M

4 (a)
Explain sample and hold circuit using op-amp.

6 M

4 (b)
What are the limitations of ideal integrator? How are they overcome in practical integrator?

6 M

Solve any one question from Q5 and Q6

5 (a)
With neat circuit diagram, explain current to voltage converter.

5 M

5 (b)
Draw the neat circuit diagram of R-2R ladder digital to analog converter (DAC) and explain its working.

5 M

5 (c)
What output voltage would be produced by a D/A converter whose output range is 0 to 10 V and input binary number is:

i) 10 (for a 2-bit DAC converter)

ii) 0110 (for a 4-bit DAC)

iii) 10111100 (for a 8-bit DAC).

i) 10 (for a 2-bit DAC converter)

ii) 0110 (for a 4-bit DAC)

iii) 10111100 (for a 8-bit DAC).

3 M

6 (a)
Explain the operation of successive approximation type analog to digital converter.

5 M

6 (b)
With neat circuit diagram, explain V to I converter with grounded load.

5 M

6 (c)
List various specification of ADC.

3 M

Solve any one question from Q7 and Q8

7 (a) (i)
Explain:

Digital phase comparator used in PLL.

Digital phase comparator used in PLL.

5 M

7 (a) (ii)
Explain:

PLL as a FSK demodulator.

PLL as a FSK demodulator.

5 M

7 (b)
For LM317 adjustable voltage regulator, R

_{1}=240 Ω and R_{=2 kΩ. If Iadj=50 μA and Vref=1.25 V. Find value of Vo.}
3 M

8 (a)
Define the following terms with reference to PLL:

i) Free running frequency

ii) Lock range

iii) Capture range

iii) Capture range

iv) Pull-in-time.

i) Free running frequency

ii) Lock range

iii) Capture range

iii) Capture range

iv) Pull-in-time.

10 M

8 (b)
Explain low drop-out regulator.

3 M

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