STUPIDSID
1 (a)
What is an Embedded Computing system? Mention its characteristics.
4 M
1 (b)
Explain Embedded system. Design process with respect to GPS moving map.
10 M
1 (c)
Draw and explain the sequence diagram for transmitting a control input in a model train controller.
6 M
2 (a)
Write ARM assembly code to implement the following C assignments
i) x=(a-b)+(c*d);
ii) y=(a<<3); (b&1b);
i) x=(a-b)+(c*d);
ii) y=(a<<3); (b&1b);
6 M
2 (b)
Explain the pipelined execution of a branch in ARM using a pipeline diagram.
4 M
2 (c)
What is cache? Explain the following with diagram.
i) Two-Level cache system
ii) Direct - Mapped cache
iii) Set - Associative cache
i) Two-Level cache system
ii) Direct - Mapped cache
iii) Set - Associative cache
10 M
3 (a)
Draw the UML state diagram of bus bridge operation and explain.
6 M
3 (b)
Explain with a neat diagram the bus with a DMA controller.
6 M
3 (c)
Write a requirement table for an Alarm clock.
8 M
4 (a)
Briefly explain Control Data Flow Graphs. Draw the CDFG for the C codes given below
i) proc1();
if (a<b)
proc2();
else
proc3();
proc4();
switch(op)
{
case 1: proc5();
break;
case 2: proc6();
breal;
case 3: proc7();
break;
}
Proc8()
ii) for (i=0; i {
a=proc1 (a,b);
b=proc2 (a,b);
}
i) proc1();
if (a<b)
proc2();
else
proc3();
proc4();
switch(op)
{
case 1: proc5();
break;
case 2: proc6();
breal;
case 3: proc7();
break;
}
Proc8()
ii) for (i=0; i
a=proc1 (a,b);
b=proc2 (a,b);
}
6 M
4 (b)
Show the contents of the Assembler's symbols Table at the end of code generation for each line of the following program.
i) ORG 100
P1 CMP r0, r1
BEQ P1
P2 CMP r0, r2
BEQ P2
P3 CMP r0, r3
BEQ P3
ii) ORG 200
P1 ADR r4, a
LDR r0, [r4]
ADR r4, e
LDR r1, [r4]
ADD r0, r0, r1
BNE q1
P2 ADR r4, e
i) ORG 100
P1 CMP r0, r1
BEQ P1
P2 CMP r0, r2
BEQ P2
P3 CMP r0, r3
BEQ P3
ii) ORG 200
P1 ADR r4, a
LDR r0, [r4]
ADR r4, e
LDR r1, [r4]
ADD r0, r0, r1
BNE q1
P2 ADR r4, e
10 M
4 (c)
Explain briefly different types of performance measures on programs.
4 M
5 (a)
What is Real-Time operating system and Real-Time Kernel? Define Task Control Block (TCB) and describe the structure of a TCB.
7 M
5 (b)
Explain the synchronization issues in resource utilization. Using the Dining Philosopher's problem. Mention the solutions for those issues.
7 M
5 (c)
Three processes with process Ids P1, P2, P3 with estimated completion time 8, 5, 4 milliseconds respectively, enters the ready queue together in the or P2, P3, P1. Process P4 with estimated execution time 4 milliseconds entered the 'Ready' queue 3 milliseconds later the start of execution of P1. Calculate the waiting time and Turn Around Time (TAT) for each process and the Average waiting time and Average Turn Around time (Assuming there is no I/O waiting for the processor in RR algorithm with Time slice=2ms.
6 M
6 (a)
Explain briefly the concept of counting semaphore and Mutex.
8 M
6 (b)
What is advanced configuration and power interface? Explain the basic global power states supported by ACPI.
6 M
6 (c)
Describe how to evaluate OS performance in terms of the following:
i) Context switching
ii) Cache scheduling
i) Context switching
ii) Cache scheduling
6 M
7 (a)
With a neat diagram, explain the various fields of CAN frame.
7 M
7 (b)
Explain a neat diagram, the structure of an IP pocket.
7 M
7 (c)
List and explain the advantages and limitations of simulator Based Debugging.
6 M
8 (a)
With a neat diagram, explain elements of the ARM AMBA bus system.
5 M
8 (b)
Write a short note on Logic Analyser.
5 M
8 (c)
Explain with a diagram the concept of Context switching, context saving and context Retrieval.
5 M
8 (d)
Differentiate Non-preemptive SJF scheduling algorithm and Preemptive SJF scheduling algorithm algorithm with simple examples.
5 M
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