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VTU Electronics and Communication Engineering (Semester 7)
DSP Algorithms & Architecture
May 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) An analog signal is sampled at the rate of 8 Khz, if 512 samples of the signal are used to compute DFT, X(k), determine the analog and digital frequency spacing between adjacent X(k) elements. Also determine analog and digital frequencies corresponding to k = 64.
6 M
1(b) List the major architectural features used in DSP system to achieve high speed program execution.
6 M
1(c) Explain the decimation and interpolation with equation. Let x(n) = [3, 2, -2, 0, 7]. It is interpolated using an interpolation filter bk = [0.5, 1, 0.5] with interpolation factor-2. Determine the interpolation sequence.
8 M

2(a) With a neat block diagram explain about the saturation logic and its use.
6 M
2(b) Briefly explain about the 4 × 4 Braun multiplier with its stracture. In n × n parallel multiplier structure how many adders are required?
8 M
2(c) With a neat block diagram, explain address generation unit of DSP system.
6 M

3(a) Compare architectural features of TMS320C25 and motarala fixed point DSP devices.
8 M
3(b) Describe the multiplice/address unit of TMS320C54XX processor with a neat block diagram.
6 M
3(c) Consider that AR3 is selected as the pointer for the circular buffer. The various register contents are Bk = 40, AR3 = 1020H, AR0= 0025H. Find : i) start and end address of the buffer ii) contents of AR3 after the execution of the instruction LD *+AR3(12H)% iii) Contents of AR3 after the instruction LD * AR3 + 0%.
8 M

4(a) Explain the operation of serial input /outputs ports and hard ware timer of TMS320C54XX on chip peripherals.
8 M
4(b) Differentiate between MAC and MACD instruction by way explaining them
4 M
4(c) By means of a figure, show the pipeline operation of the following sequence of TMS320C54XX instruction. Assume initial value of AR3 is 80h and the values. Stored in memory locations 80h, 81h, 82h as 1, 2, and 3
LD * AR3+, A
STL A, *AR3 +.
8 M

5(a) What do you mean by Q-notations used in DSP algorithm implementation? What are the values represented by 16 bit numbers N = 4000h, in Q15, Q7 and Q0 notations?
8 M
5(b) Write an assembly language program for TMS32054XX processor to multiply two Q15 numbers to produce Q15 result.
5 M
5(c) With the help of a block diagram, explain the implementation of an FIR ilter in TMS320C54XX processor. Show the memory organization for the filter implementation.
7 M

6(a) Why zero padding is done before computing the DFT?
2 M
6(b) Explain an 8-point DIT-DFT implemention structure based on the butterfly on the TMS320C54XX.
8 M
6(c) Determine optimum scaling factor to prevent over flow.
10 M

7(a) Draw the I/o interface timing diagram for read-write-read sequence of operation.
6 M
7(b) Design an interface to connect a 64k × 16 flash memory to a TMS320C54XX device. The processor address bus is A0 to A15.
6 M
7(c) What are interrupts? How interrupts are handled by the C54XX DSP processor?
8 M

8(a) Explain with a neat diagram, the synchronous serial interface between the C54XXX and a CODEC device,
6 M
8(b) Explain the operation of pulse position modulation (PPM) to encode two biomedical signals.
8 M
8(c) Describe with a suitable diagram a digital model for production of speech signal.
6 M

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