STUPIDSID
VTU Electronics and Communication Engineering (Semester 7)
DSP Algorithms & Architecture
December 2015
DSP Algorithms & Architecture
December 2015
1 (a)
What is digital signal processing? List the unique architectural features of DSP processor.
5 M
1 (b)
'FIR filter are linear phase filter'. Justify the same with magnitude and phase plots.
5 M
1 (c)
With the help of block diagram and equations explain decimation and interpolation process. Also find interpolated O/P sequence for x(n)={0, 3, 6, 9} with bx={1/3, 2/3, 1, 2/3, 1/3} and interpolation factor in 2.
10 M
2 (a)
Give the structure of 4×4 drawn multiplier explain its concept. What modification in required to carryout multiplication of signed no's? Comment on the speed of the multiplier.
8 M
2 (b)
Explain the circular and bit reversed addressing mode, with the help of algorithm.
8 M
2 (c)
What are the memory address of the operands in each of the following cases of indirect addressing model? In each case what will be the content of address register after the memory access? Assume that the initial contents of address register and the offset register are 0300h and 0020h.
i) ADD *addreg-
ii) ADD +*addreg
iii) ADD +*offset, *addreg
iv) ADD *addreg, offset
i) ADD *addreg-
ii) ADD +*addreg
iii) ADD +*offset, *addreg
iv) ADD *addreg, offset
4 M
3 (a)
Compute architecture features of TMS320C25 and ADSP2100 fixed point DSPs.
5 M
3 (b)
Explain the PMST register. Also explain the direct addressing mode of TMS320C54XX processor, with the help of a block diagram.
9 M
3 (c)
Explain the CPU unit TMS320C54XX processor with the help of functional diagram.
6 M
4 (a)
Describe the operation of the following instructions of TMS320C54XX processor with example:
i) MAC
ii) RPT
iii) MPY.
i) MAC
ii) RPT
iii) MPY.
6 M
4 (b)
Describe the operation of hardware timer with a neat diagram.
8 M
4 (c)
Write an assembly language program of TMS320C54XX processor to compute the sum of three product terms given by the equation:
y(n)= h0x(n)+h1x(n-1)+h2x(n-2), using MAC instruction.
y(n)= h0x(n)+h1x(n-1)+h2x(n-2), using MAC instruction.
6 M
5 (a)
Determine the value of each of the following 16 bit numbers represented using the given Q-notation.
i) 4400h or Q0
ii) 4400h or Q15
iii) 4400h or Q7
iv) 4400h or Q1.
i) 4400h or Q0
ii) 4400h or Q15
iii) 4400h or Q7
iv) 4400h or Q1.
6 M
5 (b)
What is an interpolation filter? Explain the implementation of digital interpolation using FIR filter and poly phase subfilter. Write the program.
8 M
5 (c)
Write a program to multiply two Q15 numbers.
6 M
6 (a) (i)
Derive the equation to implement a Butterfly structure in DITFFT algorithm.
3 M
6 (a) (ii)
How many add/subtract and multiply operations are needed to compute the butterfly structure?
3 M
6 (a) (iii)
Determine the optimum scaling factor.
3 M
6 (b) (i)
What minimum size FFT must be used to compute a DFT of 40 sample?
2 M
6 (b) (ii)
How many stages are required for FFT computation?
2 M
6 (b) (iii)
How many butterflies there per stage?
2 M
6 (b) (iv)
How many butterflies are needed for the entire computation?
2 M
6 (c)
Write the subroutine for bit reverse address generation. Explain the same.
6 M
7 (a)
Explain briefly memory space organisation in TMS320C54XX memory.
4 M
7 (b)
Describe DMA with respect to TMS320C54XX processor.
8 M
7 (c)
What are Interrupts? How interrupts are handled by the C54XX DPS processors.
8 M
8 (a)
Explain the operation of pulse position modulation (PPM) to encode two biomedical signals.
6 M
8 (b)
Write a pseudo algorithm for determining heart rate (HR) using the digital signal processor.
6 M
8 (c)
With the help of a block diagram, explain the image compression and reconstruction using JPEG encoder and decoder.
8 M
More question papers from DSP Algorithms & Architecture