SPPU Electronics and Telecom Engineering (Semester 5)
Digital Signal Processing
May 2017
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any one question from Q.1(a,b) &Q.2(a,b)
1(a) Draw the block diagram of Digital Signal Processing System and explain the Operation of each block, which additional component is needed to prevent aliasing.
4 M
1(b) Consider the analog signal Xa (t) = 3 cos2000πt+5sin6000πt+10 cos 12000πt
i) What is the Nyquist rate for this signal?
ii) If Sampling rate Fs= 5000 sample/s. What is the discrete-time signal obtained after sampling?
iii) What is the analog signal ya(t) that we can reconstruct from the samples. If was use interpolation?
6 M

2(a) Compute 4 point DFT of a sequence x(n) = {↑0,1 2 3} using Decimation In Time FFT Algorithm.
5 M
2(b) Compute the DFT of the following seqence x(n) = {↑1 2 3 4} and verify your answer using IDFT.
5 M

Solve any one question from Q.3(a,b,c) &Q.4(a,b,c)
3(a) What is the relationship between Z transform and Fourier transform.
3 M
3(b) Perform the circular convolution of the following sequence x1(n) = {↑ 1 2 3 4} x2 (n) = {uarr;2 1 2 1}
4 M
3(c) By using partial fraction method find the Inverse Z transform of \[X(z)=\frac{z^{3}}{\left ( z+1 \right )\left ( z-1 \right )^2}.\]
3 M

4(a) Show that the computational complexity is reduced if 32 point DFT is computed using Radix - 2 DIT FFT algorithm.
3 M
4(b) Compute the z transform and draw ROC of the following sequences \[\begin{align*} &i)x(n)=n^{2}u(n)\ \ \ \text{for} n\geq 0\\ &ii) x(n)= 2^{(n)}u (n-2)\end{align*}\]
3 M
4(c) Compute the Discrete Cosine Transform of the following sequence f(x) = {uarr;1 2 4 7}
4 M

Solve any one question from Q.5(a,b,c) &Q.6(a,b,c)
5(a) The system transfer function of an analog filter is given by \[H(s)=\frac{s+0.1}{(s+0.1)^2+9}\]
Using bilinear transformation method, determine the transfer function of digital filter H(z), the resonant frequency is \[W_{r}=\frac{\pi }{4}.\]
8 M
5(b) Explain the steps used for designing an IIR filter using bilinear transfomation method (BLT). What is Wraping effect in BLT?
8 M
5(c) Describe Butterworth Filters?
2 M

6(a) Obtain direct from I and II realization from a system described by \[y(n)=b_{1}x\left ( n-1 \right )+b_{2}x(n-2)+b_{3}x(n-3)-a_{1}y(n-1)-a_{2}y\left ( n-2 \right )-a_{3}y (n-3)\]
8 M
6(b) A digital filter has specifications as:
Passband frequency = wp= 0.4π,
Stopband frequency = ws = 0.6π
What are the corresponding specifications for passband and stopband frequencies in analog domain if
i) Impulse Invariance Technique is used for designing
ii) Bilinear Transformation Method id used for designing.
3 M
6(c) Write note on, " finite word length effect in IIR filter design".
4 M

Solve any one question from Q.7(a,b) &Q.8(a,b)
7(a) Justify , FIR filters are linear phase filters. Define Phase delay and Group delay in linear phase filters.
8 M
7(b) Design FIR digitial filter to approximate an ideal low pass filter with passband gain of unity, cut off frequency 850 HZ and sampling frequency 5000 HZ. The length of impluse response should be 5. Use rectangular window.
8 M

8(a) Compare the freqency domain characteristics of the different types of window Fundtions.
6 M
8(b) A low pass filter is to be designed the the following desired frequency response \( \begin{align*}H_{d}(e^{jw})= e^{-j2w} \ \text{For}-\frac{\pi }{4}\leq w\leq \frac{\pi }{4}\\ =0\ \ \ \ \ \frac{\pi }{4}<|w|< \pi \end{align*}\)/ Determine the filter coefficient hd (n) if the window function is defined as w(n) =1 0≤n≤4
=0 otherwise
Also determine the frequency reponse H (ejw) of the designed filter.
10 M

Solve any one question from Q.9(a,b) &Q.10(a,b)
9(a) Design a two stage decimator for the following specifications:
Sampling rate of an input signal = 20 KHZ
Down sampler D = 100
Passband = 0 to 40 Hz
Transition band = 40 to 50 HZ
Passband ripple = 0.01
Stopband ripple= 0.002
10 M
9(b) Explain the application of DSP to voice processing.
6 M

10(a) Draw and explaint the architectural block diagram TMS 320C 67XX series DSP Processor.
8 M
10(b) Explain the necessity of
i) MAC
ii) Barrel Shifter in Digital Signal Processors.
8 M

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