MU Instrumentation Engineering (Semester 3)
Digital Electronics
May 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Solve:
1 (a) Prove that \( (M+\overline N) + \overline L.\overline P.\overline Q. = (L+\overline P.Q)(\overline L+ M+\overline N) \)
5 M
1 (b) Implement f(ABC)=∑m(1,2,5) using 4:1 mux.
5 M
1 (c) Compare synchronous and asynchronous counter.
5 M
1 (d) What is race around condition? How to avoid it?
5 M

2 (a) Design half adder using logic gates.
5 M
2 (b) Convert in standard SOP form, y=AB+BC+AC.
5 M
2 (c) For the given logical equation,
F=AB+AC+C+AD+ABC
i) Design k-map
ii) Express is standard SOP equation.
iii) Minimize and realize the above equation using NOR gate only.
10 M

3 (a) Realize the following using 16:1 MUX and only one 8:1 MUX
f(A,B,C,D)=∑m (2, 3, 5, 7, 9, 11, 15).
10 M
3 (b) What is shift register? Explain the working of 4 bit bidirectional shift register.
10 M

4 (a) Convert JK Flip to T-Flip flop and D-Flip Flop.
10 M
4 (b) Design 4-bit Binary to Gray code converter.
10 M

5 (a) Design MOD-6 synchronous counter using JK Flip Flop.
10 M
5 (b) Design 4-bit BCD Adder using binary adder IC 7483.
10 M

Write note on (any four):
6 (a) De Morgan's Theorem.
5 M
6 (b) Noise margin and fanout digital IC's.
5 M
6 (c) PAL and PLA.
5 M
6 (d) ALU.
5 M
6 (e) Priority encoder.
5 M
6 (f) Johnson counter.
5 M



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