GTU Digital Electronics - December 2014 Exam Question Paper

GTU Electronics and Communication Engineering (Semester 3)
Digital Electronics
December 2014

Total marks: --
Total time: --

INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Select the most appropriate option.

1 (a) (i) Convert the decimal number 187 to bit binary.
(A) 10111011₂
(B) 11011101₂
(C) 10111101₂
(D) 10111100₂

1 M

1 (a) (ii) Convert the binary number 1001.0010 2 to decimal.
(A) 90.125 (B) 9.125 (C) 125 (D) 12.5

1 M

1 (a) (iii) If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?
(A) 1 (B) 2 (C) 7 (D) 8

1 M

1 (a) (iv) If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
(A) AND (B) NAND (C) NOR (D) OR

1 M

1 (a) (v) When used with an IC, what does the term "QUAD" indicate?
(A) 2 circuits
(B) 4 circuits (C) 6 circuits (D) 8 circuits

1 M

1 (a) (vi) The 2's complement of the number 1101110 is
(A) 0010001. (B) 0010001. (C) 0010010. (D) None.

1 M

1 (a) (vii) Which TTL logic gate is used for wired ANDing
(A) Open collector output
(B) Totem Pole
(C) Tri state output
(D) ECL gates

7 M

1 (b) Minimize the following logic function using K-maps and realize using NAND and NOR gates.
F(A,B,C,D) =∑_m(1,3,5,8,9,11,15) + d(2,13).

7 M

2 (a) Minimize the logic function F(A, B, C, D)=π_M(1, 2, 3, 8, 9, 10, 11, 14)⋅d(7, 15). Use Karnaugh map. Draw the logic circuit for the simplified function using NOR gates only.

7 M

Answer any one question from Q2 (b) & Q2 (c)

2 (b) Design a mod-12 Synchronous up counter using D-flipflop.

7 M

2 (c) Design a BCD to excess 3 code converter using minimum number of NAND gates

7 M

Answer any two question from Q3 (a), (b) & Q3 (c), (d)

3 (a) A combinational circuit has 3 inputs A, B, C and output F. F is true for following input combinations
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
(i) Write the Truth table for F. Use the convention True=1 and False = 0.
(ii) Write the simplified expression for F in SOP form.
(iii) Write the simplified expression for F in POS form.
(iv) Draw logic circuit using minimum number of 2-input NAND gates.

7 M

3 (b) Simplify using Boolean laws and draw the logic diagram for the given expression. \[ F= \overline{ABC}+\overline{AB}C+ \overline{A}B\overline{C} + A\overline{BC}+A\overline{B}C \]

7 M

3 (c) Prove the following Boolean identities. \[ i) \ XY+YZ+\overline{Y}Z=XY+Z \\ \\ ii) \ A.B+\overline{A}.B+\overline{A}.\overline{B}=\overline{A}+B\]

7 M

3 (d) Design a 8 to 1 multiplexer by using the four variable function given by
F(A,B,C,D) =∑m(0,1,3,4,8,9,15).

7 M

Answer any two question from Q4 (a), (b) & Q4 (c), (b)

4 (a) Draw the circuit diagrams and Truth table of all the Flip flops (SR, D, T and JK).

7 M

4 (b) Implement D flip flop using JK flip flop.

7 M

4 (c) Define the followings.
(i) Propagation delay (ii) Fan in (iii) Noise Margin (iv) Negative Logic (v) Write DeMorgan's Theorems (vi) EPROM (vii) Totem Pole output

7 M

4 (d) Compare the Followings in every aspect.
(i) TTL and CMOS
(ii) RAM and ROM

7 M

Answer any two question from Q5(a), (b) & Q5 (c), (d)

5 (a) Write short note on four bit Universal Shift Register.

7 M

5 (b) Discuss the General State machine Architecture.

7 M

5 (c) Explain the Fundamental Mode Model of Asynchronous State Machine with suitable example.

7 M

5 (d) Write short note on Programmable Logic Arrays.

7 M

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