Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Do as direct:
1 (a) (i) Convert (75)10 = (___________)2.
1 M
1 (a) (ii) Convert (101011)2 = (_________)10
1 M
1 (a) (iii) Convert (10101101)2 = (___________)16 = (__________)8
2 M
1 (a) (iv) What is self-complementing code? Represent (472)10 in 2421 self-complementing code.
2 M
1 (a) (v) Find the logic required at R input. :

1 M
1 (b) (i) Convert (96)10 to its equivalent gray code and EX-3 code.
4 M
1 (b) (ii) Perform addition in BCD format (79)BCD + (16)BCD.
3 M

2 (a) Reduce the given function using K-map and implement the same using gates. F(A,B,C,D ) = ∑m (0,1,3,7,11,15) + ∑d ( 2,4).
7 M
Answer any one question from Q2 (b) & Q2 (c)
2 (b) Design a circuit for 2-bit magnitude comparator.
7 M
2 (c) Design 3-bit even parity generator circuit.
7 M

Answer any two question from Q3 (a), (b) & Q3 (c), (d)
3 (a) (i) State De Morgan's theorems and prove with the help of truth table.
4 M
3 (a) (ii) Convert F (A, B, C) = BC +A into standard minterm form.
3 M
3 (b) Draw the truth table of full adder and implement using minimum number of logic gates.
7 M
3 (b) Draw the truth table of full subtractor and implement using minimum number of logic gates.
7 M
3 (c) (i) Discuss NAND gate as universal gate (implement NOT, AND, OR & NOR gate using NAND gate).
4 M
3 (c) (ii) Perform subtraction of (78)10 - (58)10 using 2's complement method.
3 M

Answer any two question from Q4 (a), (b) & Q4 (c), (b)
4 (a) Design 4 X 16 decoder using two 3 X 8 decoder.
7 M
4 (b) Convert D flip flop into SR flip flop.
7 M
4 (c) Implement the given function using 8 X 1 Multiplexer
F (A,B,C,D) = ∑m (0,1,2,3,5,8,9,11,14)
7 M
4 (d) With the help of function table and circuit diagram explain the working of clocked SR flip flop.
7 M

Answer any two question from Q5(a), (b) & Q5 (c), (d)
5 (a) Design 4-bit ripple counter using negative edge triggered JK flip flop.
7 M
5 (b) Compare ROM, PLA and PAL
7 M
5 (c) With neat sketch design 4-bit bidirectional shift register.
7 M
5 (d) Define followings ( i to iv with respect to logic families and v to vii with respect to finite state machine)
(i) Fan in
(ii) Fan out
(iii) Noise Margin
(iv) Propagation delay
(v) State table
(vi) Mealy machine
(vii) Moore machine
7 M



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