STUPIDSID
Short Questions
1(a)
Convert decimal number (43)10 to binary.
1 M
1(b)
Convert octal number (234)8 to hexadecimal.
1 M
1(c)
Which gates are also known as controlled NOT gate?
1 M
1(d)
Bubbled OR is also called _______
1 M
1(e)
How many selection lines are required in 32X1 MUX?
1 M
1(f)
How many enable lines are there in 3X8 decoder IC 74138?
1 M
1(g)
Define fan-out
1 M
1(h)
Which flip-flop is also known as ones-catching flip-flop?
1 M
1(i)
Which circuit is used to eliminate chattering?
1 M
1(j)
Which latch is also known as transparent latch?
1 M
1(k)
Calculate the number of state flip-flops required to generate 49 states?
1 M
1(l)
Mention two different methods used to delay the state changes sufficiently.
1 M
1(m)
What do you mean by conditional output?
1 M
1(n)
What are the advantages of asynchronous state machines?
1 M
Solved any one question from Q.2(c) & Q.2(d)
2(a)
Convert decimal number (0.252)10 to binary with an error less than 1 %.
3 M
2(b)
Minimize the following Boolean expressions.
1. X = ( (A'B'C')' + (A'B)' )'
2. Y = AB + ABC' + A'BC + A'BC'
1. X = ( (A'B'C')' + (A'B)' )'
2. Y = AB + ABC' + A'BC + A'BC'
4 M
2(c)
Implement following logic function using 8X1 MUX.
F = ∑ m(0, 1, 3, 5, 7, 11, 13, 14, 15)
F = ∑ m(0, 1, 3, 5, 7, 11, 13, 14, 15)
7 M
2(d)
Design a full adder using 3X8 decoder followed by gates.
7 M
Solved any one question from Q.3 & Q.4
3(a)
Draw & explain in brief pin diagram of 7485 four-bit magnitude comparator.
3 M
3(b)
Using D as the MEV, reduce Y = A'B'C'D' + A'B'CD' + AB'C'D' + AB'C'D + AB'CD + AB'CD'.
4 M
3(c)
Minimize following Boolean function using K-map & design the simplified function using logic gates.
F = ∑ m(1, 2, 4, 6, 7, 11, 15) + ∑ d(0, 3)
F = ∑ m(1, 2, 4, 6, 7, 11, 15) + ∑ d(0, 3)
7 M
4(a)
Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8.
3 M
4(b)
Reduce following Boolean function and then realize the reduced one using NOR gate
Only.
X = A (B'+C') (A+D)
X = A (B'+C') (A+D)
4 M
4(c)
For the figures 1, 2, & 3, plot the output waveforms referenced to the clock signal assuming the initial contents of all FFs is Q = 0. Assume all FFs are edge triggered.
7 M
Solved any one question from Q.5 & Q.6
5(a)
Draw a general model for a sequential or state machine. Also list out various types of FSMs
3 M
5(b)
1. Fill in values for S & R to cause the Q values of the SR FF given in figure 4.
| t0 | t1 | t2 | t3 | |
| S | 0 | |||
| R | 0 | |||
| Q | 1 | 0 | 0 | 1 |
2. Plot the output waveform for the inputs shown in figure 5, assuming the initial contents of the FF is Q = 0.
4 M
5(C)
Design a 3-bit synchronous up counter using K-maps and positive edge-triggered JK Ffs.
7 M
6(a)
Draw & explain in brief a high assertion input SR latch.
3 M
6(b)
Construct next state table for the state diagram given in figure 6.
4 M
6(C)
What do you mean by an output glitch problem? Explain any one method to eliminate the glitch from an OFL circuit. Draw suitable waveforms and logic diagrams.
7 M
Solved any one question from Q.7 & Q.8
7(a)
Draw & explain in brief general architecture of Xilinx FPGA.
3 M
7(b)
Explain critical race problem of an asynchronous state machines with the help of one example.
4 M
7(c)
Implement following functions using ROM.
F1 = ∑ m(1, 3, 4, 6)
F2 = ∑ m(2, 4, 5, 7)
F3 = ∑ m(0, 1, 5, 7)
F4 = ∑ m(1, 2, 3, 4)
F1 = ∑ m(1, 3, 4, 6)
F2 = ∑ m(2, 4, 5, 7)
F3 = ∑ m(0, 1, 5, 7)
F4 = ∑ m(1, 2, 3, 4)
7 M
8(a)
With the help of next state D input maps given in figure 7, construct IFL using MUXs of suitable size and number.
3 M
8(b)
Explain oscillation problem of an asynchronous state machines with the help of one example.
4 M
8(c)
Compare TTL, ECL, & CMOS logic families.
7 M
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