STUPIDSID
1 (a)
Explain drawback of synchronous counter.
5 M
1 (b)
Differentiate synchronous and asynchronous counter.
5 M
1 (c)
Draw truth table and logical diagram of half adder.
5 M
1 (d)
Explain Fan in, Fan out, power dissipation and noise immunity with reference to digital Ics.
5 M
2 (a)
Design MOD 12 asynchronous counter using T flip flop.
10 M
2 (b)
Discuss Xilinx XC 9500 CPLD architecture.
10 M
3 (a)
Design MOD-60 counter using IC 74163.
10 M
3 (b)
Analyze the sequential state machine shown in figure. Obtain state diagram for the same.
10 M
4 (a)
Simplify following logic function and realize using NAND gate
(i) F=1:m (1, 2, 4, 7, 10, 11, 13)+ d(9, 15)
(ii) F=2:m (1, 2, 3, 5, 8, 9, 11, 13, 15) + d(6).
(i) F=1:m (1, 2, 4, 7, 10, 11, 13)+ d(9, 15)
(ii) F=2:m (1, 2, 3, 5, 8, 9, 11, 13, 15) + d(6).
10 M
4 (b)
Design a Mealy type sequence detector to detect a serial input sequence of 101.
10 M
5 (a)
Draw a circuit diagram of two input TTL NAND gate and explain its operation.
10 M
5 (b)
Design 4 bit Johnson counter using J-K Flip Flop. Explain it operation using waveform.
10 M
Write a short note on.
6 (a)
Fault Model.
7 M
6 (b)
Multiplexers
7 M
6 (c)
Noise Margin.
7 M
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