STUPIDSID
1 (a)
Interfacing between CMOS and TTL.
5 M
1 (b)
Convert T flip-flop to D flip-flop.
5 M
1 (c)
XC 4000 FPGA architecture block diagram.
5 M
1 (d)
Draw truth table and logic diagram of Full subtractor
5 M
2 (a)
Write a VHDL code for Full adder.
10 M
2 (b)
Design MOD 10 asynchronous counter.
10 M
3 (a)
Design a mealy sequence detector to detect —1010-- using D flip-flops and logic gates.
10 M
3 (b)
Design a circuit with optimum utilization of PLA to implement the following functions
R=? m (0,2,5,7,11,12)
P=?m(1,3,8,9,11,13}
Q=?m(0,5,8,12,14)
R=? m (0,2,5,7,11,12)
P=?m(1,3,8,9,11,13}
Q=?m(0,5,8,12,14)
10 M
4 (a)
Implement following function using 8:1 MUX and logic gates
P (X,Y,Z,W)=? m(0,3,4,7,8,9,13,14).
P (X,Y,Z,W)=? m(0,3,4,7,8,9,13,14).
10 M
4 (b)
Eliminate redundant states and draw reduced state diagram
10 M
5 (a)
Use K-map to reduce following function and then implement it by NOR gates.
F=? M (0,3,4,5,8,10,12,14)+d(2,9)
F=? M (0,3,4,5,8,10,12,14)+d(2,9)
10 M
5 (b)
Design 8 bit up counter using IC 74163, draw a circuit diagram and explain its working.
10 M
Write short notes any three:
6 (a)
Noise Margins
7 M
6 (b)
JTAG and BIST
7 M
6 (c)
PAL and PLA
7 M
6 (d)
Stuck at '0' and '1' faults.
7 M
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