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VTU Computer Science (Semester 3)
Design of Programming with Logic
May 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Name universal gates, Realize basic gates using NAND gate only.
8 M
1(b) Prove that symmetrical signal has a duty cycle of 50% and find the frequency, low and high duty cycles for asymmetrical signal if it is high for 3 ms and low for 4 ms.
8 M
1(c) Explain the structure of VHDL/Verilog program.
4 M

2(a) Find the SOP of the following Boolean function using K-map
i) f(p q r s) = ∑m(6, 7, 9, 10, 11, 13) + d(0, 1, 8, 12)
ii) f(a b c d)= πm (1, 2, 4, 9, 10, 12) + d(0, 3, 5).
8 M
2(b) Simplify f(A B C D) = ∑m(0, 1, 2, 3, 5, 8, 12, 14, 15) using Quine - McClusky method.
12 M

3(a) Design a 16:1 multiplexer using two 8:1 multiplexer and one 2:1 multiplexer with expressions.
6 M
3(b) With relevant diagram explain explain n-bit magnitude comparator.
8 M
3(c) Give HDL implementation for 4:1 MUX using 'case' statement.
6 M

4(a) What do you mean by characteristics equation of Flip-Flop'? Draw the logic diagram, truth table and explain working of 'JK - Flip - Flop' and implement the same using NAND gate.
12 M
4(b) With state table and state transition diagram, analyse the behavior of sequential circuit shown in fig.Q.4(b). 8 M

5(a) With a neat logic and timing diagram, explain the working of a 4-bit SISO register.
10 M
5(b) Design two 4-bit number serial adder.
6 M
5(c) Write verilog HDL code for 4-bit SIPO shift register.
4 M

6(a) Design synchronous modulus - 5(mod-5) counter using JK-Flip-Flop.
10 M
6(b) Explain, design of 4-bit bu=inary ripple - up counter using negative edge triggered JK-Flip-Flops with block diagram and timing diagram.
10 M

7(a) With neat diagram explain and compare Mealay and Moore machine.
10 M
7(b) Reduce state transition diagram (Moore model) of Fig.Q.7(b) by i) Row elimination method ii) Implication table method. 10 M

8(a) Discuss the two drawbacks of resistive divider used in converting D/A. Draw the schematic for a 4-bit binary ladder and explain how the digital to analog conversion is achieved using it.
10 M
8(b) Discuss the working of following A/D converters:
i) Successive approximation A/D
ii) Counter type A/D.
10 M

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