1 (a)
What is Logic gate? State and prove De Morgan's theorems.

7 M

1 (b)
Describe positive and negative logic. Prove 'positive OR' logic equal to ?Negative AND? logic.

5 M

1 (c)
Implement the following functions by using: i) NAND gates only. Y= ((A+B)⋅C)⋅

8 M

2 (a)
Find the minimal SOP and minimal POS of the following Boolean function using K-Map. f(a, b, c, d) = ∑

_{m}(6, 7, 9, 10, 13) + d(1, 4, 5, 11).
8 M

2 (b)
Using Q.M. method simplify the following expression and realize it by using NAND logic only. f(a, b, c, d)=∑(0, 3, 5, 6, 7, 11, 14).

10 M

2 (c)
Write a note on Static Hazard.

2 M

3 (a)
Construct 8:1 multiplexer using only 2:1 multiplexer.

6 M

3 (b)
Mention the three differences between decoder and demultiplexer.

3 M

3 (c)
Write the four comparisons between PLA and PAL.

4 M

3 (d)
Implement the following functions using PLA:

A(x, y, z)=∑m (1, 2, 4, 6):

B(x, y, z)=∑m(0, 1, 6, 7):

C(x, y, z) = ∑m(2, 6).

A(x, y, z)=∑m (1, 2, 4, 6):

B(x, y, z)=∑m(0, 1, 6, 7):

C(x, y, z) = ∑m(2, 6).

7 M

4 (a)
With logic diagram and truth table, explain the working of master slave (J, K) flip flop.

6 M

4 (b)
Draw the logic truth table and timing diagram of positive edge triggered D-flip flop.

6 M

4 (c)
Write the Verilog code for positive edge triggered J.K. flip flop.

3 M

4 (d)
With neat diagram, explain the working principles of Switch De bouncer circuit.

5 M

5 (a)
Write a note on classifications of Registers.

4 M

5 (b)
With neat diagram and timing diagram, explain the working of Serial in - Serial out register. For explanation construct 4 bit register using J.K flip flops.

10 M

5 (c)
Write a Verilog code for: i) Switched tail counter ii) Shift registers of 5 bits constructed using D-flip flops.

6 M

6 (a)
Write the comparison between Synchronous and Asynchronous counter.

4 M

6 (b)
Design: i) a divided by 78 counter using 7493 and 7492 IC ii) modulo 120 counter using 7490 and 7492 IC.

8 M

6 (c)
Design a mod 6 counter using J.K flip flop and k-map simplification method.

8 M

7 (a)
Explain the difference between Mealy model and Moore model.

5 M

7 (b)
Design a Mealy type sequence detector to detect a serial i/p sequence of 101.

10 M

7 (c)
How does state transition diagram of Moore machine differ from Mealy machine?

5 M

8 (a)
Explain with neat diagram, successive approximation A/D converter.

6 M

8 (b)
Explain with neat diagram, counter method of A/D conversion.

6 M

8 (c)
Write short notes on:

i) Binary loader

ii) Differences between D/A and A/D converters.

i) Binary loader

ii) Differences between D/A and A/D converters.

8 M

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