STUPIDSID
1 (a)
Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:
M1: 16k words, 50ns access time
M2: 1m words, 400ns access time
Assume 8 words cache blocks and set size of 256 words with the set associative mapping
(i) Show the mapping between M1 and M2
(ii) Calculate the effective access time with a cache hit ratio of h=0.95
M1: 16k words, 50ns access time
M2: 1m words, 400ns access time
Assume 8 words cache blocks and set size of 256 words with the set associative mapping
(i) Show the mapping between M1 and M2
(ii) Calculate the effective access time with a cache hit ratio of h=0.95
10 M
1 (b)
What do you mean by fetch cycle, instruction cycle, machine cycle and interrupt acknowledgement cycle? Explain in brief.
10 M
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10 M
2 (b)
What is micro operation? Give some examples of four types of micro-operations.
10 M
3 (a)
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3 (b)
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10 M
4 (a)
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10 M
4 (b)
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10 M
5 (a)
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10 M
5 (b)
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10 M
6 (a)
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10 M
6 (b)
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10 M
Write short notes on (any four)
7 (a)
PCI bus architecture
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7 (b)
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7 (c)
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5 M
7 (d)
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7 (e)
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