MU Information Technology (Semester 4)
Computer Organization and Architecture
December 2014
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Solve any four:
1 (a) What are the types of pipeline hazards?
5 M
1 (b) Explain in brief memory mapped I/O.
5 M
1 (c) Explain in detail cache coherence.
5 M
1 (d) Draw flow chart of Booth's algorithm.
5 M
1 (e) Define stored program concept and draw Von Neumann's Architecture.
5 M

2 (a) Explain in detail different types of addressing modes.
10 M
2 (b) Multiply (-2)10 and (-5)10 using Booth's Algorithm.
10 M

3 (a) Explain Wilke's Engine (Hard-wired Control Unit) in detail.
10 M
3 (b) Explain virtual memory with reference to memory hierarchy, segments and pages.
10 M

4 (a) Explain features of RISC and CISC processors.
10 M
4 (b) Explain six stage instruction pipeline with suitable diagram.
10 M

5 (a) Explain various high speed memories such as interleaved memories and caches.
10 M
5 (b) Explain LRU page replacement policy with suitable example.
10 M

6 (a) What is Bus Arbitration? Explain any two techniques of Bus Arbitration.
10 M
Write a short note (any two):
6 (b)(i)

Nano programming

5 M
6 (b)(ii)

DMA (Direct Memory Access)

5 M
6 (b)(iii) Plotter
5 M



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