SPPU Computer Engineering (Semester 3)
Computer Organization
December 2016
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any one question fromQ.1(a,b) and Q.2(a,b)
1(a) Show the general structure of IAS computer and explain in detail.
6 M
1(b) Explain folllowing cache mapping techiques along with their merits and demerits:
i) Direct
ii) Set associative.
6 M

2(a) Perform Divison of following numbers using restoring Divison Algorithm:
Dividend = 1011 Divisor = 011.
6 M
2(b) What is Cache coherence? What are the solutions to cache coherence porblem in signle CPU system.
6 M

Solve any one question fromQ3(a,b) and Q.4(a,b)
3(a) What are the evolutionary steps of I/O channel? Explain types of I/O channel?
6 M
3(b) Explain the following addressing modes with one example each:
i) Immediate
ii) Register Indirect
iii) Direct.
6 M

4(a) Differentiate between Programmed I/O and interrrupt driven I/O.
6 M
4(b) What is diplacement addressing? Explain its types with calclulation of effective address.
6 M

Solve any one question fromQ5(a,b) and Q.6(a,b)
5(a) What are various hazards in instruction pipelining? Explain with example.
7 M
5(b) What is register organization? What are different types of registers? Explain in detail.
6 M

6(a) Explain the instruction cycle in detail.
6 M
6(b) List and explain various ways in which an instruction pipleine can deal with conditional branch istructions.
7 M

Solve any one question fromQ.7(a,b) and Q.8(a,b)
7(a) Compare horiziontal and vertical microinstruction format.
6 M
7(b) Write a control sequence for the following instruction for single bus organization:
SUB (R3), R1.
7 M

8(a) Compare Hardwired control over micro-programmed control.
6 M
8(b) Explain in detail micro instruction sequencing organization.
7 M

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