SPPU Information Technology (Semester 6)
Systems Programming
December 2016
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any one question from Q.1(a,b) & Q.2(a,b)
1(a) Show the contents of various tables alongwith stack organization generated by the II pass macro processor for the following code. Also give the code after expansion.


     EVAL&X, &Y, &Z

     AIF (&YEQ&Z). ONLY


     SUB & Y

     ADD & Z

     AGO    .OVER




     MAJOR     &P,&Q,&R,&M,&N,&L

     EVAL        &P&Q&R

     STORE      &L

     EVAL  &M,&N&N



      MAJOR  A,B,C,D,E,F

A    DS  1

B    DS  2

C    DS  3

D    DS  4

E    DS  5

F    DS   6



8 M
1(b) Define the following terms with examples.
i) Compiler ii) Loader
iii) Assembler iv) Macroprocessor
2 M

2(a) Give the various data structures in the design of pass-1 and pass-2 of a Two-pass direct linking loader for the given example.


PGA   START                0

ENTRY PGAI                10

EXTRN PGB                 20

DC A(PGA),(PGB+4)     30  



PGB     START                                             0

            ENTRY PGB1                                  5

            EXTRN PGA                                   10                              

PGB1 DC   A(PGB 1)                                   14

PGB2 DC   A(PGB+4), A(PGB1-PGB)           18

PGB3 DC   A(PGB-PGA-16)                          22


8 M
2(b) Explain the different phases of a complier.
2 M

Solve any one question from Q.3(a,b) & Q.4(a,b)
3(a) Perform Pass I and Pass II for the given assembly language code and assume a hypothetical instruction set with each instruction of length 1

           START  500

           MOVER AREG, LAB

           ADD BREG, LOOP

L1       DS 20

           LOAD AREG,='5'

           ADD  BREG,='1'


L2         SUB CREG, LAB


             MOVEM AREG, LAB

             ORIGIN L2

             SUB BREG, ='2'

LAB       DC2

LOOP     DS5



8 M
3(b) Explain the concept of subroutine linkages in loaders and linkers.
2 M

4(a) Write a note on overlay structure of loaders.
4 M
4(b) Convert the given regular expression of DFA:
6 M

Solve any one question from Q.5(a,b,c) & Q.6(a,b,c)
5(a) Differentiate between top down parser and bottom up parser.
4 M
5(b) For the given grammar, design predictive parser and show parsing table. S→+SS/*SS/ a and parse the string+*aaa. Justify
8 M
5(c) Using the given table perform operator precedence parser for the expression id+id*id
6 M

6(a) Compare SLR and table driven parsing methods.
4 M
6(b) Define Handle and handle pruning w.r.t bottom up parser. For the grammar given, S→SS+/SS*/a. Identify the handles at each step and parse the string aaa*a++.
4 M
6(c) Design SLR parser for the given grammar. Also show the moves by the parser for input string "a/(a+a)*a".
S→S+S/SS/ (s)/ S*S/a
10 M

Solve any one question from Q.7(a,b) & Q.8(a,b)
7(a) Define and explain annotated parse tree for the given grammar
E→E+T / T
T→ T*F / F
Annotate the tree for 2+3*5
8 M
7(b) Which are the different types of intermediate code representations. Explain w.r.t the expression.
8 M

8(a) Draw the dependency graph of the expression in Q7a) and list down the synthesized and inherited attributes with definition.
8 M
8(b) Write the method of generating intermediate code for the expression
If(condition) then p= q+r
Else x= y+z
8 M

Solve any one question from Q.9(a,b,c) & Q.10(a,b)
9(a) Obtain the TAC for the following code.
8 M
9(b) Discuss code generation issues
4 M
9(c) Write a short note on activation record.
4 M

10(a) Discuss with suitable example machine dependent code optimization.
8 M
10(b) Explain the following code optimization techniques with examples.
i) Removal of Loop Invariants
ii) Elimination of common sub expressions
iii) Dead code Elimination
iv) Copy Propagation
8 M

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