STUPIDSID
1 (a)
Draw and explain timing diagram for read operation in minimum mode of 8086.
5 M
1 (b)
Explain I/O related addressing mode of 8086.
5 M
1 (c)
Write down features of super SPARC processor.
5 M
1 (d)
Enlist the instruction pairing rules for U and V pipeline in Pentium.
5 M
2 (a)
Explain address translation mechanism used in protected mode of 83086.
10 M
2 (b)
Write assembly language program for 8086 to exchange contents of two memory blocks.
10 M
3 (a)
Design 8086 microprocessor based system with following specifications
(a) Microprocessor 8086 working at 10 Mhz in minimum mode
(b) 32 KB EPROM using 8KB chips
(c) 16 KB SRAM using 4KB chips
Explain the design along with memory address map.
(a) Microprocessor 8086 working at 10 Mhz in minimum mode
(b) 32 KB EPROM using 8KB chips
(c) 16 KB SRAM using 4KB chips
Explain the design along with memory address map.
10 M
3 (b)
Explain how the flushing of pipeline problem is minimized in Pentium architecture.
10 M
4 (a)
Interface DMA controller 8237 with 8086 microprocessor. Explain different data transfer modes of 8237 DMA controller.
10 M
4 (b)
Differentiate between real mode and protected mode.
10 M
5 (a)
Draw & explain block diagram of 8259 PIC.
10 M
5 (b)
Draw a segment descriptor and explain different fields.
10 M
Write short note on any four:
6 (a)
Code cache organization of Pentium.
5 M
6 (b)
State the use of RF, TF, VM, NT, IOPL flag bits.
5 M
6 (c)
Data types supported by SPARC processor.
5 M
6 (d)
Advantages of memory segmentation in 8086.
5 M
6 (e)
Maximum mode of 8086
5 M
6 (f)
Control word register of 8255.
5 M
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